Initial DevGen plan

Here is the initial design draft from 2001 for DevGen, the preprocessor that evolved into DML 1.0 in 2005.

Generate code for register access:
----------------------------------

M - Mandatory
O - Optional
 
* A register needs at least one fields.

* For a register bank specify:
+ [M] Name
+ [M] Overlapping access to register ok?

* For a register specify:
+ [M] Name
+ [M] Address (offset)
+ [M] Size
+ [O] Partial access ok?
+ [O] Don't generate access code
+ [O] Configuration attribute?
+ [O] Debug - category (new), level, string, log always/changes

* For a register field specify: (simplify if only field in register?)
+ [M] Name
+ [M] Position in register
+ [M] RO/RW/WO/W1C/CoR/Trig/...
+ [M] Reset value (hard, soft)
+ [O] Configuration attribute support?
+ [O] Debug - category (new), level, string, log always/changes
+ [O] Way to specify conditional RO
+ [O] Field that must be written with specified value (0 or 1 typically).
+ [O] Signed

* How to support split fields? (including fields with parts in different regs).

* Support special endian handling?

* Some way to specify actions that are triggered by a register access.

Generated code include:
* read/write access code for registers
* checks to verify that accesses are ok (warn if not)
* debug_log() calls
* configuration attribute get/set functions
* Register reset function.

More generated code:
--------------------

* Specify "interfaces" to implement, and get empty functions.

* init_local() with interface, class, and attribute registrations.

* Generated code should allow C inheritance (used by pci devices).
  Perhaps also support it? Cleaner when used with Mathilda.

* Get/set macros for registers and register fields.

Other features:
---------------

* Delayed assignments. Example: "irq_line = 1 after 10ms;"
  Implement by hiding event queue code.

* "Script thread" equivalent. I.e. wait for some event to occur
  in the middle of sequential code. Could be difficult to
  implement properly (must work with checkpointing, etc).

* Should devgen know about Simics PCI system?

* Support to make state-machine writing simpler.
  + Verify illegal state changes.