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[RTGTest] Add some arithmetic instructions
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@maerhart
maerhart committed Jan 31, 2025
1 parent b73d2d7 commit e9ca920
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Showing 4 changed files with 127 additions and 1 deletion.
55 changes: 55 additions & 0 deletions include/circt/Dialect/RTGTest/IR/RTGTestOps.td
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Original file line number Diff line number Diff line change
Expand Up @@ -187,6 +187,50 @@ class InstFormatBOpBase<string mnemonic, int opcode7, int funct3>
}];
}

class InstFormatROpBase<string mnemonic, int opcode7, int funct3, int funct7>
: RTGTestOp<"rv32i." # mnemonic, [InstructionOpAdaptor]> {

let arguments = (ins IntegerRegisterType:$rd,
IntegerRegisterType:$rs1,
IntegerRegisterType:$rs2);

let assemblyFormat = "$rd `,` $rs1 `,` $rs2 attr-dict";

let extraClassDefinition = [{
void $cppClass::printInstructionBinary(llvm::raw_ostream &os,
FoldAdaptor adaptor) {
auto rd = cast<rtg::RegisterAttrInterface>(adaptor.getRd());
auto rs1 = cast<rtg::RegisterAttrInterface>(adaptor.getRs1());
auto rs2 = cast<rtg::RegisterAttrInterface>(adaptor.getRs2());

auto binary = llvm::APInt(7, }] # funct7 # [{)
.concat(llvm::APInt(5, rs2.getClassIndex()))
.concat(llvm::APInt(5, rs1.getClassIndex()))
.concat(llvm::APInt(3, }] # funct3 # [{))
.concat(llvm::APInt(5, rd.getClassIndex()))
.concat(llvm::APInt(7, }] # opcode7 # [{));

SmallVector<char> str;
binary.toStringUnsigned(str, 16);
os << str;
}

void $cppClass::printInstructionAssembly(llvm::raw_ostream &os,
FoldAdaptor adaptor) {
os << getOperationName().rsplit('.').second
<< " "
<< cast<rtg::RegisterAttrInterface>(adaptor.getRd())
.getRegisterAssembly()
<< ", "
<< cast<rtg::RegisterAttrInterface>(adaptor.getRs1())
.getRegisterAssembly()
<< ", "
<< cast<rtg::RegisterAttrInterface>(adaptor.getRs2())
.getRegisterAssembly();
}
}];
}

//===- Instructions -------------------------------------------------------===//

def RV32I_JALROp : InstFormatIOpBase<"jalr", 0b1100111, 0b000>;
Expand All @@ -204,5 +248,16 @@ def RV32I_LWOp : InstFormatIOpBase<"lw", 0b0000011, 0b010>;
def RV32I_LBUOp : InstFormatIOpBase<"lbu", 0b0000011, 0b100>;
def RV32I_LHUOp : InstFormatIOpBase<"lhu", 0b0000011, 0b101>;

def RV32I_ADD : InstFormatROpBase<"add", 0b110011, 0b000, 0b0000000>;
def RV32I_SUB : InstFormatROpBase<"sub", 0b110011, 0b000, 0b0100000>;
def RV32I_SLL : InstFormatROpBase<"sll", 0b110011, 0b001, 0b0000000>;
def RV32I_SLT : InstFormatROpBase<"slt", 0b110011, 0b010, 0b0000000>;
def RV32I_SLTU : InstFormatROpBase<"sltu", 0b110011, 0b011, 0b0000000>;
def RV32I_XOR : InstFormatROpBase<"xor", 0b110011, 0b100, 0b0000000>;
def RV32I_SRL : InstFormatROpBase<"srl", 0b110011, 0b101, 0b0000000>;
def RV32I_SRA : InstFormatROpBase<"sra", 0b110011, 0b101, 0b0100000>;
def RV32I_OR : InstFormatROpBase<"or", 0b110011, 0b110, 0b0000000>;
def RV32I_AND : InstFormatROpBase<"and", 0b110011, 0b111, 0b0000000>;

def RV32I_ECALLOp : InstFormatIImmOpBase<"ecall", 0b1110011, 0b000000000000>;
def RV32I_EBREAKOp : InstFormatIImmOpBase<"ebreak", 0b1110011, 0b000000000001>;
50 changes: 50 additions & 0 deletions test/Dialect/RTG/Transform/emit-rtg-isa-assembly.mlir
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Original file line number Diff line number Diff line change
Expand Up @@ -81,6 +81,56 @@ rtg.test @test0 : !rtg.dict<> {
// CHECK-NEXT: # bgeu ra, s0, 6144
// CHECK-NEXT: .word 0x8080F0E3
rtgtest.rv32i.bgeu %rd, %rs, %imm13 : !rtgtest.imm13

// CHECK-ALLOWED-NEXT: add ra, s0, s0
// CHECK-NEXT: # add ra, s0, s0
// CHECK-NEXT: .word 0x8400B3
rtgtest.rv32i.add %rd, %rs, %rs

// CHECK-ALLOWED-NEXT: sub ra, s0, s0
// CHECK-NEXT: # sub ra, s0, s0
// CHECK-NEXT: .word 0x408400B3
rtgtest.rv32i.sub %rd, %rs, %rs

// CHECK-ALLOWED-NEXT: sll ra, s0, s0
// CHECK-NEXT: # sll ra, s0, s0
// CHECK-NEXT: .word 0x8410B3
rtgtest.rv32i.sll %rd, %rs, %rs

// CHECK-ALLOWED-NEXT: slt ra, s0, s0
// CHECK-NEXT: # slt ra, s0, s0
// CHECK-NEXT: .word 0x8420B3
rtgtest.rv32i.slt %rd, %rs, %rs

// CHECK-ALLOWED-NEXT: sltu ra, s0, s0
// CHECK-NEXT: # sltu ra, s0, s0
// CHECK-NEXT: .word 0x8430B3
rtgtest.rv32i.sltu %rd, %rs, %rs

// CHECK-ALLOWED-NEXT: xor ra, s0, s0
// CHECK-NEXT: # xor ra, s0, s0
// CHECK-NEXT: .word 0x8440B3
rtgtest.rv32i.xor %rd, %rs, %rs

// CHECK-ALLOWED-NEXT: srl ra, s0, s0
// CHECK-NEXT: # srl ra, s0, s0
// CHECK-NEXT: .word 0x8450B3
rtgtest.rv32i.srl %rd, %rs, %rs

// CHECK-ALLOWED-NEXT: sra ra, s0, s0
// CHECK-NEXT: # sra ra, s0, s0
// CHECK-NEXT: .word 0x408450B3
rtgtest.rv32i.sra %rd, %rs, %rs

// CHECK-ALLOWED-NEXT: or ra, s0, s0
// CHECK-NEXT: # or ra, s0, s0
// CHECK-NEXT: .word 0x8460B3
rtgtest.rv32i.or %rd, %rs, %rs

// CHECK-ALLOWED-NEXT: and ra, s0, s0
// CHECK-NEXT: # and ra, s0, s0
// CHECK-NEXT: .word 0x8470B3
rtgtest.rv32i.and %rd, %rs, %rs
}

// CHECK-EMPTY:
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2 changes: 1 addition & 1 deletion test/Dialect/RTG/Transform/unsupported-instr.txt
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@@ -1 +1 @@
rtgtest.rv32i.jalr,rtgtest.rv32i.lb,rtgtest.rv32i.lh,rtgtest.rv32i.lw,rtgtest.rv32i.lbu,rtgtest.rv32i.lhu,rtgtest.rv32i.beq,rtgtest.rv32i.bne,rtgtest.rv32i.blt,rtgtest.rv32i.bge,rtgtest.rv32i.bltu,rtgtest.rv32i.bgeu
rtgtest.rv32i.jalr,rtgtest.rv32i.lb,rtgtest.rv32i.lh,rtgtest.rv32i.lw,rtgtest.rv32i.lbu,rtgtest.rv32i.lhu,rtgtest.rv32i.beq,rtgtest.rv32i.bne,rtgtest.rv32i.blt,rtgtest.rv32i.bge,rtgtest.rv32i.bltu,rtgtest.rv32i.bgeu,rtgtest.rv32i.add,rtgtest.rv32i.sub,rtgtest.rv32i.sll,rtgtest.rv32i.slt,rtgtest.rv32i.sltu,rtgtest.rv32i.xor,rtgtest.rv32i.srl,rtgtest.rv32i.sra,rtgtest.rv32i.or,rtgtest.rv32i.and
21 changes: 21 additions & 0 deletions test/Dialect/RTGTest/IR/basic.mlir
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Expand Up @@ -142,6 +142,27 @@ rtg.test @instructions : !rtg.dict<imm: !rtgtest.imm12, imm13: !rtgtest.imm13, l
rtgtest.rv32i.bltu %rd, %rs, %label : !rtg.label
// CHECK: rtgtest.rv32i.bgeu [[RD]], [[RS]], [[LABEL]] : !rtg.label
rtgtest.rv32i.bgeu %rd, %rs, %label : !rtg.label

// CHECK: rtgtest.rv32i.add [[RD]], [[RS]], [[RS]] {rtg.some_attr}
rtgtest.rv32i.add %rd, %rs, %rs {rtg.some_attr}
// CHECK: rtgtest.rv32i.sub [[RD]], [[RS]], [[RS]] {rtg.some_attr}
rtgtest.rv32i.sub %rd, %rs, %rs {rtg.some_attr}
// CHECK: rtgtest.rv32i.sll [[RD]], [[RS]], [[RS]] {rtg.some_attr}
rtgtest.rv32i.sll %rd, %rs, %rs {rtg.some_attr}
// CHECK: rtgtest.rv32i.slt [[RD]], [[RS]], [[RS]] {rtg.some_attr}
rtgtest.rv32i.slt %rd, %rs, %rs {rtg.some_attr}
// CHECK: rtgtest.rv32i.sltu [[RD]], [[RS]], [[RS]] {rtg.some_attr}
rtgtest.rv32i.sltu %rd, %rs, %rs {rtg.some_attr}
// CHECK: rtgtest.rv32i.xor [[RD]], [[RS]], [[RS]] {rtg.some_attr}
rtgtest.rv32i.xor %rd, %rs, %rs {rtg.some_attr}
// CHECK: rtgtest.rv32i.srl [[RD]], [[RS]], [[RS]] {rtg.some_attr}
rtgtest.rv32i.srl %rd, %rs, %rs {rtg.some_attr}
// CHECK: rtgtest.rv32i.sra [[RD]], [[RS]], [[RS]] {rtg.some_attr}
rtgtest.rv32i.sra %rd, %rs, %rs {rtg.some_attr}
// CHECK: rtgtest.rv32i.or [[RD]], [[RS]], [[RS]] {rtg.some_attr}
rtgtest.rv32i.or %rd, %rs, %rs {rtg.some_attr}
// CHECK: rtgtest.rv32i.and [[RD]], [[RS]], [[RS]] {rtg.some_attr}
rtgtest.rv32i.and %rd, %rs, %rs {rtg.some_attr}
}

// -----
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