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[hw,prim_ram_1p,rtl] Add reset input to prim_ram_1p #3823

[hw,prim_ram_1p,rtl] Add reset input to prim_ram_1p

[hw,prim_ram_1p,rtl] Add reset input to prim_ram_1p #3823

Triggered via pull request December 24, 2024 16:08
Status Success
Total duration 2h 14m 5s
Artifacts 31

ci.yml

on: pull_request
Earl Grey for CW310  /  Build bitstream
1h 3m
Earl Grey for CW310 / Build bitstream
Earl Grey for CW310 Hyperdebug  /  Build bitstream
1h 7m
Earl Grey for CW310 Hyperdebug / Build bitstream
Earl Grey for CW340  /  Build bitstream
1h 30m
Earl Grey for CW340 / Build bitstream
Lint (slow)
11m 35s
Lint (slow)
Build documentation
4m 53s
Build documentation
Airgapped build
8m 49s
Airgapped build
Verible lint
1m 6s
Verible lint
Run OTBN smoke Test
2m 40s
Run OTBN smoke Test
Run OTBN crypto tests
23m 44s
Run OTBN crypto tests
Verilated English Breakfast
8m 19s
Verilated English Breakfast
Verilated Earl Grey
1h 17m
Verilated Earl Grey
CW305's Bitstream
21m 32s
CW305's Bitstream
Build Docker Containers
2m 38s
Build Docker Containers
Build and test software
15m 49s
Build and test software
CW310 Test ROM Tests  /  FPGA test
5m 18s
CW310 Test ROM Tests / FPGA test
CW310 ROM Tests  /  FPGA test
38m 27s
CW310 ROM Tests / FPGA test
CW310 ROM_EXT Tests  /  FPGA test
7m 57s
CW310 ROM_EXT Tests / FPGA test
CW310 SiVal Tests  /  FPGA test
24m 55s
CW310 SiVal Tests / FPGA test
CW310 SiVal ROM_EXT Tests  /  FPGA test
35m 7s
CW310 SiVal ROM_EXT Tests / FPGA test
CW310 Manufacturing Tests  /  FPGA test
31m 28s
CW310 Manufacturing Tests / FPGA test
CW340 Test ROM Tests  /  FPGA test
3m 42s
CW340 Test ROM Tests / FPGA test
CW340 ROM Tests  /  FPGA test
46s
CW340 ROM Tests / FPGA test
CW340 ROM_EXT Tests  /  FPGA test
5m 34s
CW340 ROM_EXT Tests / FPGA test
CW340 SiVal Tests  /  FPGA test
15m 46s
CW340 SiVal Tests / FPGA test
CW340 SiVal ROM_EXT Tests  /  FPGA test
3m 36s
CW340 SiVal ROM_EXT Tests / FPGA test
CW340 Manufacturing Tests  /  FPGA test
37m 8s
CW340 Manufacturing Tests / FPGA test
Cache bitstreams to GCP
0s
Cache bitstreams to GCP
Verify FPGA jobs
21s
Verify FPGA jobs
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8 errors
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Process completed with exit code 1.
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Some target names have banned characters.
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Process completed with exit code 1.
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Process completed with exit code 1.
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Countermeasure check failed.
Lint (slow)
Process completed with exit code 1.
Build and test software
Process completed with exit code 1.

Artifacts

Produced during runtime
Name Size
chip_englishbreakfast_cw305
1.37 MB
execute_manuf_fpga_tests_cw310-targets
623 Bytes
execute_manuf_fpga_tests_cw310-test-results
58.8 KB
execute_manuf_fpga_tests_cw340-targets
594 Bytes
execute_manuf_fpga_tests_cw340-test-results
54.1 KB
execute_rom_ext_fpga_tests_cw310-targets
519 Bytes
execute_rom_ext_fpga_tests_cw310-test-results
12.6 KB
execute_rom_ext_fpga_tests_cw340-targets
437 Bytes
execute_rom_ext_fpga_tests_cw340-test-results
7.11 KB
execute_rom_fpga_tests_cw310-targets
1.75 KB
execute_rom_fpga_tests_cw310-test-results
46.1 KB
execute_rom_fpga_tests_cw340-targets
162 Bytes
execute_rom_fpga_tests_cw340-test-results
201 Bytes
execute_sival_fpga_tests_cw310-targets
784 Bytes
execute_sival_fpga_tests_cw310-test-results
36.8 KB
execute_sival_fpga_tests_cw340-targets
502 Bytes
execute_sival_fpga_tests_cw340-test-results
39.9 KB
execute_sival_rom_ext_fpga_tests_cw310-targets
2.21 KB
execute_sival_rom_ext_fpga_tests_cw310-test-results
180 KB
execute_sival_rom_ext_fpga_tests_cw340-targets
435 Bytes
execute_sival_rom_ext_fpga_tests_cw340-test-results
17.2 KB
execute_test_rom_fpga_tests_cw310-targets
312 Bytes
execute_test_rom_fpga_tests_cw310-test-results
2.91 KB
execute_test_rom_fpga_tests_cw340-targets
258 Bytes
execute_test_rom_fpga_tests_cw340-test-results
44.3 KB
partial-build-bin-chip_earlgrey_cw310
6.01 MB
partial-build-bin-chip_earlgrey_cw310_hyperdebug
6.02 MB
partial-build-bin-chip_earlgrey_cw340
10 MB
sw_build_test-test-results
75.7 KB
verilated_englishbreakfast
6.48 MB
verilator_earlgrey-test-results
8.88 KB