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[hw,prim_ram_1p,rtl] Add reset input to prim_ram_1p #3823

[hw,prim_ram_1p,rtl] Add reset input to prim_ram_1p

[hw,prim_ram_1p,rtl] Add reset input to prim_ram_1p #3823

CW310 SiVal Tests  /  FPGA test

succeeded Dec 24, 2024 in 24m 55s
Set up job
1s
Run actions/checkout@v4
14s
Prepare environment
19s
Download bitstream
3s
Update hyperdebug firmware
1m 24s
Execute tests
22m 36s
Publish Bazel test results
12s
Upload target pattern file
1s
Post Prepare environment
0s
Post Run actions/checkout@v4
0s
Complete job
0s