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Add Exclusive Adapter (openhwgroup#187)
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* Add atomic adapter as submodule

* Change UART frequency

* Add atomic memory adapter

* Bump AXI exclusive submodule version

* Re-name ariane_next to ariane-dev

* Switch to official `atop` branch on `axi_node`
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@zarubaf
zarubaf committed Mar 18, 2019
1 parent b1bdc0c commit 8433003
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3 changes: 3 additions & 0 deletions .gitmodules
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Expand Up @@ -40,3 +40,6 @@
[submodule "fpga/src/ariane-ethernet"]
path = fpga/src/ariane-ethernet
url = https://github.com/lowRISC/ariane-ethernet.git
[submodule "src/axi_riscv_atomics"]
path = src/axi_riscv_atomics
url = https://github.com/pulp-platform/axi_riscv_atomics.git
4 changes: 2 additions & 2 deletions .travis.yml
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Expand Up @@ -41,7 +41,7 @@ env:
branches:
only:
- master
- ariane_next
- ariane-dev

before_install:
- export CXX=g++-7 CC=gcc-7
Expand Down Expand Up @@ -72,7 +72,7 @@ jobs:
name: build gcc
script:
- ci/build-riscv-gcc.sh 1
- rm -rf $RISCV/riscv-gnu-toolchain
- rm -rf $RISCV/riscv-gnu-toolchain
- stage: compile2
name: build tools
script:
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1 change: 1 addition & 0 deletions Makefile
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Expand Up @@ -90,6 +90,7 @@ src := $(filter-out src/ariane_regfile.sv, $(wildcard src/*.sv)) \
$(wildcard fpga/src/axi_slice/src/*.sv) \
$(wildcard src/plic/*.sv) \
$(wildcard src/axi_node/src/*.sv) \
$(wildcard src/axi_riscv_atomics/src/*.sv) \
$(wildcard src/axi_mem_if/src/*.sv) \
$(filter-out src/debug/dm_pkg.sv, $(wildcard src/debug/*.sv)) \
$(wildcard src/debug/debug_rom/*.sv) \
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112 changes: 67 additions & 45 deletions fpga/src/ariane_xilinx.sv
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Expand Up @@ -209,7 +209,8 @@ axi_node_wrap_with_slices #(
ariane_soc::EthernetBase + ariane_soc::EthernetLength -1,
ariane_soc::GPIOBase + ariane_soc::GPIOLength - 1,
ariane_soc::DRAMBase + ariane_soc::DRAMLength - 1
})
}),
.valid_rule_i ('1)
);

// ---------------
Expand Down Expand Up @@ -446,51 +447,72 @@ logic s_axi_rlast;
logic s_axi_rvalid;
logic s_axi_rready;

assign master[ariane_soc::DRAM].r_user = '0;
assign master[ariane_soc::DRAM].b_user = '0;
AXI_BUS #(
.AXI_ADDR_WIDTH ( AxiAddrWidth ),
.AXI_DATA_WIDTH ( AxiDataWidth ),
.AXI_ID_WIDTH ( AxiIdWidthSlaves ),
.AXI_USER_WIDTH ( AxiUserWidth )
) dram();

axi_riscv_atomics #(
.AXI_ADDR_WIDTH ( AxiAddrWidth ),
.AXI_DATA_WIDTH ( AxiDataWidth ),
.AXI_ID_WIDTH ( AxiIdWidthSlaves ),
.AXI_USER_WIDTH ( AxiUserWidth ),
.AXI_MAX_WRITE_TXNS ( 1 ),
.RISCV_WORD_WIDTH ( 64 )
) i_axi_riscv_atomics (
.clk_i ( clk ),
.rst_ni ( ndmreset_n ),
.slv ( master[ariane_soc::DRAM] ),
.mst ( dram )
);

assign dram.r_user = '0;
assign dram.b_user = '0;

xlnx_axi_clock_converter i_xlnx_axi_clock_converter_ddr (
.s_axi_aclk ( clk ),
.s_axi_aresetn ( ndmreset_n ),
.s_axi_awid ( master[ariane_soc::DRAM].aw_id ),
.s_axi_awaddr ( master[ariane_soc::DRAM].aw_addr ),
.s_axi_awlen ( master[ariane_soc::DRAM].aw_len ),
.s_axi_awsize ( master[ariane_soc::DRAM].aw_size ),
.s_axi_awburst ( master[ariane_soc::DRAM].aw_burst ),
.s_axi_awlock ( master[ariane_soc::DRAM].aw_lock ),
.s_axi_awcache ( master[ariane_soc::DRAM].aw_cache ),
.s_axi_awprot ( master[ariane_soc::DRAM].aw_prot ),
.s_axi_awregion ( master[ariane_soc::DRAM].aw_region ),
.s_axi_awqos ( master[ariane_soc::DRAM].aw_qos ),
.s_axi_awvalid ( master[ariane_soc::DRAM].aw_valid ),
.s_axi_awready ( master[ariane_soc::DRAM].aw_ready ),
.s_axi_wdata ( master[ariane_soc::DRAM].w_data ),
.s_axi_wstrb ( master[ariane_soc::DRAM].w_strb ),
.s_axi_wlast ( master[ariane_soc::DRAM].w_last ),
.s_axi_wvalid ( master[ariane_soc::DRAM].w_valid ),
.s_axi_wready ( master[ariane_soc::DRAM].w_ready ),
.s_axi_bid ( master[ariane_soc::DRAM].b_id ),
.s_axi_bresp ( master[ariane_soc::DRAM].b_resp ),
.s_axi_bvalid ( master[ariane_soc::DRAM].b_valid ),
.s_axi_bready ( master[ariane_soc::DRAM].b_ready ),
.s_axi_arid ( master[ariane_soc::DRAM].ar_id ),
.s_axi_araddr ( master[ariane_soc::DRAM].ar_addr ),
.s_axi_arlen ( master[ariane_soc::DRAM].ar_len ),
.s_axi_arsize ( master[ariane_soc::DRAM].ar_size ),
.s_axi_arburst ( master[ariane_soc::DRAM].ar_burst ),
.s_axi_arlock ( master[ariane_soc::DRAM].ar_lock ),
.s_axi_arcache ( master[ariane_soc::DRAM].ar_cache ),
.s_axi_arprot ( master[ariane_soc::DRAM].ar_prot ),
.s_axi_arregion ( master[ariane_soc::DRAM].ar_region ),
.s_axi_arqos ( master[ariane_soc::DRAM].ar_qos ),
.s_axi_arvalid ( master[ariane_soc::DRAM].ar_valid ),
.s_axi_arready ( master[ariane_soc::DRAM].ar_ready ),
.s_axi_rid ( master[ariane_soc::DRAM].r_id ),
.s_axi_rdata ( master[ariane_soc::DRAM].r_data ),
.s_axi_rresp ( master[ariane_soc::DRAM].r_resp ),
.s_axi_rlast ( master[ariane_soc::DRAM].r_last ),
.s_axi_rvalid ( master[ariane_soc::DRAM].r_valid ),
.s_axi_rready ( master[ariane_soc::DRAM].r_ready ),
.s_axi_aclk ( clk ),
.s_axi_aresetn ( ndmreset_n ),
.s_axi_awid ( dram.aw_id ),
.s_axi_awaddr ( dram.aw_addr ),
.s_axi_awlen ( dram.aw_len ),
.s_axi_awsize ( dram.aw_size ),
.s_axi_awburst ( dram.aw_burst ),
.s_axi_awlock ( dram.aw_lock ),
.s_axi_awcache ( dram.aw_cache ),
.s_axi_awprot ( dram.aw_prot ),
.s_axi_awregion ( dram.aw_region ),
.s_axi_awqos ( dram.aw_qos ),
.s_axi_awvalid ( dram.aw_valid ),
.s_axi_awready ( dram.aw_ready ),
.s_axi_wdata ( dram.w_data ),
.s_axi_wstrb ( dram.w_strb ),
.s_axi_wlast ( dram.w_last ),
.s_axi_wvalid ( dram.w_valid ),
.s_axi_wready ( dram.w_ready ),
.s_axi_bid ( dram.b_id ),
.s_axi_bresp ( dram.b_resp ),
.s_axi_bvalid ( dram.b_valid ),
.s_axi_bready ( dram.b_ready ),
.s_axi_arid ( dram.ar_id ),
.s_axi_araddr ( dram.ar_addr ),
.s_axi_arlen ( dram.ar_len ),
.s_axi_arsize ( dram.ar_size ),
.s_axi_arburst ( dram.ar_burst ),
.s_axi_arlock ( dram.ar_lock ),
.s_axi_arcache ( dram.ar_cache ),
.s_axi_arprot ( dram.ar_prot ),
.s_axi_arregion ( dram.ar_region ),
.s_axi_arqos ( dram.ar_qos ),
.s_axi_arvalid ( dram.ar_valid ),
.s_axi_arready ( dram.ar_ready ),
.s_axi_rid ( dram.r_id ),
.s_axi_rdata ( dram.r_data ),
.s_axi_rresp ( dram.r_resp ),
.s_axi_rlast ( dram.r_last ),
.s_axi_rvalid ( dram.r_valid ),
.s_axi_rready ( dram.r_ready ),
// to size converter
.m_axi_aclk ( ddr_clock_out ),
.m_axi_aresetn ( ndmreset_n ),
Expand Down Expand Up @@ -548,7 +570,7 @@ xlnx_clk_gen i_xlnx_clk_gen (
fan_ctrl i_fan_ctrl (
.clk_i ( clk ),
.rst_ni ( ndmreset_n ),
.pwm_setting_i ( sw[3:0] ),
.pwm_setting_i ( '1 ),
.fan_pwm_o ( fan_pwm )
);

Expand Down
15 changes: 9 additions & 6 deletions include/axi_intf.sv
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Expand Up @@ -31,6 +31,7 @@ interface AXI_BUS #(
typedef logic [AXI_DATA_WIDTH-1:0] data_t;
typedef logic [AXI_STRB_WIDTH-1:0] strb_t;
typedef logic [AXI_USER_WIDTH-1:0] user_t;
typedef logic [5:0] atop_t;

id_t aw_id;
addr_t aw_addr;
Expand All @@ -41,6 +42,7 @@ interface AXI_BUS #(
cache_t aw_cache;
prot_t aw_prot;
qos_t aw_qos;
atop_t aw_atop;
region_t aw_region;
user_t aw_user;
logic aw_valid;
Expand Down Expand Up @@ -82,15 +84,15 @@ interface AXI_BUS #(
logic r_ready;

modport Master (
output aw_id, aw_addr, aw_len, aw_size, aw_burst, aw_lock, aw_cache, aw_prot, aw_qos, aw_region, aw_user, aw_valid, input aw_ready,
output aw_id, aw_addr, aw_len, aw_size, aw_burst, aw_lock, aw_cache, aw_prot, aw_qos, aw_atop, aw_region, aw_user, aw_valid, input aw_ready,
output w_data, w_strb, w_last, w_user, w_valid, input w_ready,
input b_id, b_resp, b_user, b_valid, output b_ready,
output ar_id, ar_addr, ar_len, ar_size, ar_burst, ar_lock, ar_cache, ar_prot, ar_qos, ar_region, ar_user, ar_valid, input ar_ready,
input r_id, r_data, r_resp, r_last, r_user, r_valid, output r_ready
);

modport Slave (
input aw_id, aw_addr, aw_len, aw_size, aw_burst, aw_lock, aw_cache, aw_prot, aw_qos, aw_region, aw_user, aw_valid, output aw_ready,
input aw_id, aw_addr, aw_len, aw_size, aw_burst, aw_lock, aw_cache, aw_prot, aw_qos, aw_atop, aw_region, aw_user, aw_valid, output aw_ready,
input w_data, w_strb, w_last, w_user, w_valid, output w_ready,
output b_id, b_resp, b_user, b_valid, input b_ready,
input ar_id, ar_addr, ar_len, ar_size, ar_burst, ar_lock, ar_cache, ar_prot, ar_qos, ar_region, ar_user, ar_valid, output ar_ready,
Expand All @@ -99,7 +101,7 @@ interface AXI_BUS #(

/// The interface as an output (issuing requests, initiator, master).
modport out (
output aw_id, aw_addr, aw_len, aw_size, aw_burst, aw_lock, aw_cache, aw_prot, aw_qos, aw_region, aw_user, aw_valid, input aw_ready,
output aw_id, aw_addr, aw_len, aw_size, aw_burst, aw_lock, aw_cache, aw_prot, aw_qos, aw_atop, aw_region, aw_user, aw_valid, input aw_ready,
output w_data, w_strb, w_last, w_user, w_valid, input w_ready,
input b_id, b_resp, b_user, b_valid, output b_ready,
output ar_id, ar_addr, ar_len, ar_size, ar_burst, ar_lock, ar_cache, ar_prot, ar_qos, ar_region, ar_user, ar_valid, input ar_ready,
Expand All @@ -108,7 +110,7 @@ interface AXI_BUS #(

/// The interface as an input (accepting requests, target, slave).
modport in (
input aw_id, aw_addr, aw_len, aw_size, aw_burst, aw_lock, aw_cache, aw_prot, aw_qos, aw_region, aw_user, aw_valid, output aw_ready,
input aw_id, aw_addr, aw_len, aw_size, aw_burst, aw_lock, aw_cache, aw_prot, aw_qos, aw_atop, aw_region, aw_user, aw_valid, output aw_ready,
input w_data, w_strb, w_last, w_user, w_valid, output w_ready,
output b_id, b_resp, b_user, b_valid, input b_ready,
input ar_id, ar_addr, ar_len, ar_size, ar_burst, ar_lock, ar_cache, ar_prot, ar_qos, ar_region, ar_user, ar_valid, output ar_ready,
Expand Down Expand Up @@ -140,6 +142,7 @@ interface AXI_BUS_ASYNC
logic [3:0] aw_cache;
logic [2:0] aw_prot;
logic [3:0] aw_qos;
logic [5:0] aw_atop;
logic [3:0] aw_region;
logic [AXI_USER_WIDTH-1:0] aw_user;
logic [BUFFER_WIDTH-1:0] aw_writetoken;
Expand Down Expand Up @@ -181,15 +184,15 @@ interface AXI_BUS_ASYNC
logic [BUFFER_WIDTH-1:0] r_readpointer;

modport Master (
output aw_id, aw_addr, aw_len, aw_size, aw_burst, aw_lock, aw_cache, aw_prot, aw_qos, aw_region, aw_user, aw_writetoken, input aw_readpointer,
output aw_id, aw_addr, aw_len, aw_size, aw_burst, aw_lock, aw_cache, aw_prot, aw_qos, aw_atop, aw_region, aw_user, aw_writetoken, input aw_readpointer,
output w_data, w_strb, w_last, w_user, w_writetoken, input w_readpointer,
input b_id, b_resp, b_user, b_writetoken, output b_readpointer,
output ar_id, ar_addr, ar_len, ar_size, ar_burst, ar_lock, ar_cache, ar_prot, ar_qos, ar_region, ar_user, ar_writetoken, input ar_readpointer,
input r_id, r_data, r_resp, r_last, r_user, r_writetoken, output r_readpointer
);

modport Slave (
input aw_id, aw_addr, aw_len, aw_size, aw_burst, aw_lock, aw_cache, aw_prot, aw_qos, aw_region, aw_user, aw_writetoken, output aw_readpointer,
input aw_id, aw_addr, aw_len, aw_size, aw_burst, aw_lock, aw_cache, aw_prot, aw_qos, aw_atop, aw_region, aw_user, aw_writetoken, output aw_readpointer,
input w_data, w_strb, w_last, w_user, w_writetoken, output w_readpointer,
output b_id, b_resp, b_user, b_writetoken, input b_readpointer,
input ar_id, ar_addr, ar_len, ar_size, ar_burst, ar_lock, ar_cache, ar_prot, ar_qos, ar_region, ar_user, ar_writetoken, output ar_readpointer,
Expand Down
2 changes: 1 addition & 1 deletion src/axi
Submodule axi updated 16 files
+1 −0 Bender.yml
+4 −1 CHANGELOG.md
+1 −0 include/axi/assign.svh
+317 −0 src/axi_atop_filter.sv
+4 −0 src/axi_cut.sv
+1 −0 src/axi_id_remap.sv
+8 −6 src/axi_intf.sv
+1 −0 src/axi_join.sv
+1 −0 src/axi_lite_to_axi.sv
+1 −0 src/axi_modify_address.sv
+20 −0 src/axi_pkg.sv
+6 −0 src/axi_test.sv
+1 −0 src_files.yml
+2 −0 test/tb_axi_delayer.sv
+1 −0 test/tb_axi_lite_to_axi.wave.do
+1 −0 test/tb_axi_to_axi_lite.wave.do
2 changes: 1 addition & 1 deletion src/axi_node
Submodule axi_node updated 14 files
+3 −5 Bender.yml
+18 −30 src/axi_AR_allocator.sv
+122 −145 src/axi_AW_allocator.sv
+0 −300 src/axi_ArbitrationTree.sv
+46 −54 src/axi_BR_allocator.sv
+38 −51 src/axi_BW_allocator.sv
+0 −114 src/axi_FanInPrimitive_Req.sv
+0 −74 src/axi_RR_Flag_Req.sv
+4 −0 src/axi_node.sv
+70 −0 src/axi_node_arbiter.sv
+14 −22 src/axi_node_intf_wrap.sv
+13 −9 src/axi_node_wrap_with_slices.sv
+4 −0 src/axi_request_block.sv
+1 −3 src_files.yml
1 change: 1 addition & 0 deletions src/axi_riscv_atomics
Submodule axi_riscv_atomics added at 90729d
1 change: 1 addition & 0 deletions src/util/axi_master_connect.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -26,6 +26,7 @@ module axi_master_connect (
assign master.aw_cache = axi_req_i.aw.cache;
assign master.aw_prot = axi_req_i.aw.prot;
assign master.aw_qos = axi_req_i.aw.qos;
assign master.aw_atop = axi_req_i.aw.atop;
assign master.aw_region = axi_req_i.aw.region;
assign master.aw_user = '0;
assign master.aw_valid = axi_req_i.aw_valid;
Expand Down
2 changes: 1 addition & 1 deletion src/util/axi_slave_connect.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -17,7 +17,6 @@ module axi_slave_connect (
AXI_BUS.in slave
);

assign axi_req_o.aw.atop = '0; // not supported at the moment
assign axi_req_o.aw.id = slave.aw_id;
assign axi_req_o.aw.addr = slave.aw_addr;
assign axi_req_o.aw.len = slave.aw_len;
Expand All @@ -27,6 +26,7 @@ module axi_slave_connect (
assign axi_req_o.aw.cache = slave.aw_cache;
assign axi_req_o.aw.prot = slave.aw_prot;
assign axi_req_o.aw.qos = slave.aw_qos;
assign axi_req_o.aw.atop = slave.aw_atop;
assign axi_req_o.aw.region = slave.aw_region;
// assign = slave.aw_user;
assign axi_req_o.aw_valid = slave.aw_valid;
Expand Down
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