added includes directory

nguyendao-uom · Feb 22, 2022 · 0f93045 · 0f93045
1 parent d99dcd5
commit 0f93045
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Showing 4 changed files with 12 additions and 1 deletion.
diff --git a/verilog/dv/Makefile b/verilog/dv/Makefile
@@ -34,7 +34,7 @@ $(DV_PATTERNS): verify-% :
 
 clean:  ${PATTERNS}
 	for i in ${PATTERNS}; do \
-		( cd $$i && make clean ) ; \
+		( cd $$i && \rm  -f *.elf *.hex *.bin *.vvp *.log *.vcd *.lst *.hexe ) ; \
 	done
 	rm -rf *.log
 

diff --git a/verilog/includes/includes.gl+sdf.caravel_user_project b/verilog/includes/includes.gl+sdf.caravel_user_project
@@ -0,0 +1,3 @@
+// Caravel user project includes		
+$USER_PROJECT_VERILOG/gl/user_project_wrapper.v	     
+$USER_PROJECT_VERILOG/gl/user_proj_example.v
diff --git a/verilog/includes/includes.gl.caravel_user_project b/verilog/includes/includes.gl.caravel_user_project
@@ -0,0 +1,3 @@
+# Caravel user project includes	     
+-v $(USER_PROJECT_VERILOG)/gl/user_project_wrapper.v	     
+-v $(USER_PROJECT_VERILOG)/gl/user_proj_example.v     
diff --git a/verilog/includes/includes.rtl.caravel_user_project b/verilog/includes/includes.rtl.caravel_user_project
@@ -0,0 +1,5 @@
+# Caravel user project includes
+-v $(USER_PROJECT_VERILOG)/rtl/user_project_wrapper.v	     
+-v $(USER_PROJECT_VERILOG)/rtl/user_proj_example.v
+
+