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Added illegal instruction exception decoding on unused Imm6 bits for some SIMD instructions. #985

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merged 4 commits into from
Apr 18, 2024

RTL cleanup for SiemensEDA Tessent.

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Merged

Added illegal instruction exception decoding on unused Imm6 bits for some SIMD instructions. #985

RTL cleanup for SiemensEDA Tessent.
46dc9b5
Select commit
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succeeded Apr 18, 2024 in 14s