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all standard rv32i components implemented for egui
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@onsdagens
onsdagens committed Oct 11, 2023
1 parent 868b3e5 commit 5347af9
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Showing 13 changed files with 951 additions and 23 deletions.
37 changes: 36 additions & 1 deletion riscv/examples/empty.rs
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Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
use clap::Parser;
use riscv::components::*;
use std::{collections::BTreeMap, path::PathBuf, rc::Rc};
use std::{cell::RefCell, collections::BTreeMap, path::PathBuf, rc::Rc};
use syncrim::common::{ComponentStore, Input};

#[derive(Parser, Debug)]
Expand Down Expand Up @@ -53,6 +53,41 @@ fn main() {
ctrl: dummy.clone(),
enable: dummy.clone(),
}),
Rc::new(Decoder {
width: DECODER_WIDTH,
height: DECODER_HEIGHT,
id: "dummy_decoder".to_string(),
pos: (0.0, 0.0),
instruction: dummy.clone(),
}),
Rc::new(LSBZero {
height: LSB_ZERO_HEIGHT,
width: LSB_ZERO_WIDTH,
id: "dummy_lsbzero".to_string(),
pos: (0.0, 0.0),
data_i: dummy.clone(),
}),
Rc::new(RegFile {
id: "dummy_reg_file".into(),
pos: (0.0, 0.0),
width: REG_FILE_WIDTH,
height: REG_FILE_HEIGHT,
read_addr1: dummy.clone(),
read_addr2: dummy.clone(),
write_data: dummy.clone(),
write_addr: dummy.clone(),
write_enable: dummy.clone(),
registers: RegStore::new(Rc::new(RefCell::new([0; 32]))),
history: RegHistory::new(),
}),
Rc::new(SZExt {
height: SIGN_ZERO_EXT_HEIGHT,
width: SIGN_ZERO_EXT_WIDTH,
id: "dummy_szext".to_string(),
pos: (0.0, 0.0),
data_i: dummy.clone(),
sel_i: dummy.clone(),
}),
],
};
let library = syncrim::gui_egui::editor::Library(lib.store);
Expand Down
14 changes: 10 additions & 4 deletions riscv/examples/riscv.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -89,8 +89,8 @@ fn main() {
Input::new("jalr_se", "out"),
),
Rc::new(BranchLogic {
width: 60.0,
height: 60.0,
width: BRANCH_LOGIC_WIDTH,
height: BRANCH_LOGIC_HEIGHT,
id: "branch_logic".to_string(),
pos: (725.0, 300.0),
rs1: Input::new("reg_file", "reg_a"),
Expand All @@ -99,6 +99,8 @@ fn main() {
enable: Input::new("decoder", "branch_logic_enable"),
}),
Rc::new(LSBZero {
height: LSB_ZERO_HEIGHT,
width: LSB_ZERO_WIDTH,
id: "jalr_stripper".to_string(),
pos: (600.0, 1000.0),
data_i: Input::new("jalr_adder", "out"),
Expand Down Expand Up @@ -140,14 +142,16 @@ fn main() {
32,
),
Rc::new(InstrMem {
width: 200.0,
height: 100.0,
width: INSTR_MEM_WIDTH,
height: INSTR_MEM_HEIGHT,
id: "instr_mem".to_string(),
pos: (180.0, 400.0),
pc: Input::new("reg", "out"),
bytes: instr_mem,
}),
Rc::new(Decoder {
width: DECODER_WIDTH,
height: DECODER_HEIGHT,
id: "decoder".to_string(),
pos: (300.0, 150.0),
instruction: Input::new("instr_mem", "instruction"),
Expand All @@ -163,6 +167,8 @@ fn main() {
Input::new("decoder", "regfile_rd"),
),
Rc::new(SZExt {
height:SIGN_ZERO_EXT_HEIGHT,
width: SIGN_ZERO_EXT_WIDTH,
id: "imm_szext".to_string(),
pos: (450.0, 1000.0),
data_i: Input::new("decoder", "sign_zero_ext_data"),
Expand Down
36 changes: 35 additions & 1 deletion riscv/src/components/decoder.rs
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Original file line number Diff line number Diff line change
@@ -1,7 +1,11 @@
use log::trace;
use serde::{Deserialize, Serialize};
#[cfg(feature = "gui-egui")]
use std::rc::Rc;
#[cfg(feature = "gui-egui")]
use syncrim::common::EguiComponent;
use syncrim::common::{
Component, Condition, Input, InputPort, OutputType, Ports, SignalValue, Simulator,
Component, Condition, Id, Input, InputPort, OutputType, Ports, SignalValue, Simulator,
};
use syncrim::components::MemCtrl;

Expand Down Expand Up @@ -30,8 +34,13 @@ pub const DECODER_BRANCH_LOGIC_CTL_ID: &str = "branch_logic_ctl";
pub const DECODER_BRANCH_LOGIC_ENABLE_ID: &str = "branch_logic_enable";
pub const DECODER_JALR_IMM_ID: &str = "jalr_imm";

pub const DECODER_HEIGHT: f32 = 200.0;
pub const DECODER_WIDTH: f32 = 30.0;

#[derive(Serialize, Deserialize)]
pub struct Decoder {
pub width: f32,
pub height: f32,
pub id: String,
pub pos: (f32, f32),

Expand All @@ -43,6 +52,23 @@ impl Component for Decoder {
fn to_(&self) {
println!("Decoder");
}
#[cfg(feature = "gui-egui")]
fn dummy(&self, id: &str, pos: (f32, f32)) -> Box<Rc<dyn EguiComponent>> {
let dummy_input = Input::new("dummy", "out");
Box::new(Rc::new(Decoder {
width: DECODER_WIDTH,
height: DECODER_HEIGHT,
id: id.to_string(),
pos: (pos.0, pos.1),
instruction: dummy_input,
}))
}
fn set_id_port(&mut self, target_port_id: Id, new_input: Input) {
match target_port_id.as_str() {
DECODER_INSTRUCTION_ID => self.instruction = new_input,
_ => (),
}
}
fn get_id_ports(&self) -> (String, Ports) {
(
self.id.clone(),
Expand Down Expand Up @@ -487,6 +513,8 @@ mod test {
store: vec![
Rc::new(ProbeOut::new("instruction")),
Rc::new(Decoder {
width: 0.0,
height: 0.0,
id: "decoder".to_string(),
pos: (0.0, 0.0),
instruction: Input::new("instruction", "out"),
Expand Down Expand Up @@ -1083,6 +1111,8 @@ mod test {
store: vec![
Rc::new(ProbeOut::new("instruction")),
Rc::new(Decoder {
width: 0.0,
height: 0.0,
id: "decoder".to_string(),
pos: (0.0, 0.0),
instruction: Input::new("instruction", "out"),
Expand Down Expand Up @@ -1602,6 +1632,8 @@ mod test {
store: vec![
Rc::new(ProbeOut::new("instruction")),
Rc::new(Decoder {
width: 0.0,
height: 0.0,
id: "decoder".to_string(),
pos: (0.0, 0.0),
instruction: Input::new("instruction", "out"),
Expand Down Expand Up @@ -2145,6 +2177,8 @@ mod test {
store: vec![
Rc::new(ProbeOut::new("instruction")),
Rc::new(Decoder {
width: 0.0,
height: 0.0,
id: "decoder".to_string(),
pos: (0.0, 0.0),
instruction: Input::new("instruction", "out"),
Expand Down
31 changes: 29 additions & 2 deletions riscv/src/components/lsb_zero.rs
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Original file line number Diff line number Diff line change
@@ -1,15 +1,23 @@
use serde::{Deserialize, Serialize};
#[cfg(feature = "gui-egui")]
use std::rc::Rc;
#[cfg(feature = "gui-egui")]
use syncrim::common::EguiComponent;
use syncrim::{
common::{Component, Condition, Input, InputPort, OutputType, Ports, Simulator},
common::{Component, Condition, Id, Input, InputPort, OutputType, Ports, Simulator},
signal::SignalValue,
};

pub const LSB_ZERO_DATA_I_ID: &str = "data_i";

pub const LSB_ZERO_OUT_ID: &str = "out";

pub const LSB_ZERO_HEIGHT: f32 = 10.0;
pub const LSB_ZERO_WIDTH: f32 = 10.0;

#[derive(Serialize, Deserialize)]
pub struct LSBZero {
pub height: f32,
pub width: f32,
pub id: String,
pub pos: (f32, f32),

Expand All @@ -21,6 +29,23 @@ impl Component for LSBZero {
fn to_(&self) {
println!("LSBZero");
}
#[cfg(feature = "gui-egui")]
fn dummy(&self, id: &str, pos: (f32, f32)) -> Box<Rc<dyn EguiComponent>> {
let dummy = Input::new("dummy", "out");
Box::new(Rc::new(LSBZero {
height: LSB_ZERO_HEIGHT,
width: LSB_ZERO_WIDTH,
id: id.to_string(),
pos: (pos.0, pos.1),
data_i: dummy.clone(),
}))
}
fn set_id_port(&mut self, target_port_id: Id, new_input: Input) {
match target_port_id.as_str() {
LSB_ZERO_DATA_I_ID => self.data_i = new_input,
_ => (),
}
}
fn get_id_ports(&self) -> (String, Ports) {
(
self.id.clone(),
Expand Down Expand Up @@ -63,6 +88,8 @@ mod test {
store: vec![
Rc::new(ProbeOut::new("input")),
Rc::new(LSBZero {
height: 0.0,
width: 0.0,
id: "lzero".to_string(),
pos: (0.0, 0.0),
data_i: Input::new("input", "out"),
Expand Down
36 changes: 33 additions & 3 deletions riscv/src/components/reg_file.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -3,11 +3,12 @@ use num_enum::TryFromPrimitive;
use serde::{Deserialize, Serialize};
use std::ops::{Deref, Range};
use std::{cell::RefCell, rc::Rc};
#[cfg(feature = "gui-egui")]
use syncrim::common::EguiComponent;
use syncrim::common::{
Component, Condition, Input, InputPort, OutputType, Ports, SignalUnsigned, Simulator,
Component, Condition, Id, Input, InputPort, OutputType, Ports, SignalUnsigned, Simulator,
};
use syncrim::signal::SignalValue;

#[allow(non_camel_case_types)]
#[rustfmt::skip]
#[derive(Copy, Clone, Debug, TryFromPrimitive)]
Expand Down Expand Up @@ -56,6 +57,9 @@ pub const REG_FILE_WRITE_ENABLE_ID: &str = "write_enable";
pub const REG_FILE_REG_A_OUT: &str = "reg_a";
pub const REG_FILE_REG_B_OUT: &str = "reg_b";

pub const REG_FILE_WIDTH: f32 = 250.0;
pub const REG_FILE_HEIGHT: f32 = 500.0;

#[derive(Serialize, Deserialize, Clone)]
pub struct RegFile {
pub id: String,
Expand Down Expand Up @@ -188,7 +192,33 @@ impl Component for RegFile {
},
)
}

#[cfg(feature = "gui-egui")]
fn dummy(&self, id: &str, pos: (f32, f32)) -> Box<Rc<dyn EguiComponent>> {
let dummy_input = Input::new("dummy", "out");
Box::new(Rc::new(RegFile {
width: REG_FILE_WIDTH,
height: REG_FILE_HEIGHT,
id: id.to_string(),
pos: (pos.0, pos.1),
registers: RegStore::new(Rc::new(RefCell::new([0; 32]))),
history: RegHistory::new(),
read_addr1: dummy_input.clone(),
read_addr2: dummy_input.clone(),
write_data: dummy_input.clone(),
write_addr: dummy_input.clone(),
write_enable: dummy_input.clone(),
}))
}
fn set_id_port(&mut self, target_port_id: Id, new_input: Input) {
match target_port_id.as_str() {
REG_FILE_READ_ADDR1_ID => self.read_addr1 = new_input,
REG_FILE_READ_ADDR2_ID => self.read_addr2 = new_input,
REG_FILE_WRITE_DATA_ID => self.write_data = new_input,
REG_FILE_WRITE_ADDR_ID => self.write_addr = new_input,
REG_FILE_WRITE_ENABLE_ID => self.write_enable = new_input,
_ => (),
}
}
fn clock(&self, simulator: &mut Simulator) -> Result<(), Condition> {
if simulator.get_input_value(&self.write_enable) == (true as SignalUnsigned).into() {
let data = simulator.get_input_value(&self.write_data);
Expand Down
45 changes: 37 additions & 8 deletions riscv/src/components/sign_zero_ext.rs
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Original file line number Diff line number Diff line change
@@ -1,16 +1,24 @@
use log::trace;
use serde::{Deserialize, Serialize};
#[cfg(feature = "gui-egui")]
use std::rc::Rc;
#[cfg(feature = "gui-egui")]
use syncrim::common::EguiComponent;
use syncrim::common::{
Component, Condition, Input, InputPort, OutputType, Ports, SignalValue, Simulator,
Component, Condition, Id, Input, InputPort, OutputType, Ports, SignalValue, Simulator,
};

pub const SIGN_ZERO_EXT_DATA_I_ID: &str = "data_i";
pub const SIGN_ZERO_EXT_SEL_I_ID: &str = "sel_i";

pub const SIGN_ZERO_EXT_OUT_ID: &str = "out";

pub const SIGN_ZERO_EXT_HEIGHT: f32 = 30.0;
pub const SIGN_ZERO_EXT_WIDTH: f32 = 60.0;

#[derive(Serialize, Deserialize)]
pub struct SZExt {
pub height: f32,
pub width: f32,
pub id: String,
pub pos: (f32, f32),

Expand All @@ -23,6 +31,25 @@ impl Component for SZExt {
fn to_(&self) {
println!("s_z_ext");
}
#[cfg(feature = "gui-egui")]
fn dummy(&self, id: &str, pos: (f32, f32)) -> Box<Rc<dyn EguiComponent>> {
let dummy = Input::new("dummy", "out");
Box::new(Rc::new(SZExt {
height: SIGN_ZERO_EXT_HEIGHT,
width: SIGN_ZERO_EXT_WIDTH,
id: id.to_string(),
pos: (pos.0, pos.1),
data_i: dummy.clone(),
sel_i: dummy.clone(),
}))
}
fn set_id_port(&mut self, target_port_id: Id, new_input: Input) {
match target_port_id.as_str() {
SIGN_ZERO_EXT_DATA_I_ID => self.data_i = new_input,
SIGN_ZERO_EXT_SEL_I_ID => self.sel_i = new_input,
_ => (),
}
}
fn get_id_ports(&self) -> (String, Ports) {
(
self.id.clone(),
Expand Down Expand Up @@ -91,12 +118,14 @@ mod test {
Rc::new(ProbeOut::new("input")),
Rc::new(ProbeOut::new("sel")),
Rc::new(SZExt {
id: "szext".to_string(),
pos: (0.0, 0.0),
data_i: Input::new("input", "out"),
sel_i: Input::new("sel", "out"),
}),
],
height: 0.0,
width: 0.0,
id: "szext".to_string(),
pos: (0.0, 0.0),
data_i: Input::new("input", "out"),
sel_i: Input::new("sel", "out"),
}),
],
};

let mut simulator = Simulator::new(cs).unwrap();
Expand Down
2 changes: 1 addition & 1 deletion riscv/src/gui_egui/components/branch_logic.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -167,7 +167,7 @@ impl EguiComponent for BranchLogic {
}

fn top_padding(&self) -> f32 {
20f32
self.height / 2f32
}

fn set_pos(&mut self, pos: (f32, f32)) {
Expand Down
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