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fpga: Added ddr4 and vcu128 flow, added draft of Vivado IP simulation…
… flow fpga: Added VIOs Connect VIO-generated reset signal to dram wrapper fpga: Support of zcu102 fpga: zcu102.xdc constraint file added fpga: zcu102 changed phy and added firsts constraints fpga: Switching to clk_wiz and xilinx.mk fpga: Testing ddr4 fpga: Start working on SPI driver fpga: SD card test fpga: Rolled-back SD fpga: Add vcu128 ci Co-Authored-By: Yann Picod <[email protected]>
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@@ -27,6 +27,47 @@ make all | |
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If you have access to our internal servers, you can run `make nonfree-init` to fetch additional resources we cannot make publically accessible. Note that these are *not required* to use anything provided in this repository. | ||
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## Linux image | ||
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To build the Linux image for FPGA: | ||
```bash | ||
# Clone and build GCC, OpenSBI, U-Boot and Linux | ||
git clone [email protected]:pulp-platform/cva6-sdk.git --branch fix/cheshire | ||
cd cva6-sdk | ||
git submodule update --init --recursive | ||
make images | ||
# Link the output in the sw dir | ||
ln -s cva6-sdk/install64 sw/boot/install64 | ||
# Build the image at sw/boot/linux-[genesys2,vcu128].gpt.bin | ||
make BOARD=[genesys2,vcu128] chs-linux-img | ||
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``` | ||
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On Genesys2, you can now flash this image to your sd card (require sudo). | ||
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```bash | ||
# Replace sdX by your SD card device | ||
dd if=sw/boot/cheshire-linux-genesys2.gpt.bin of=/dev/sdX | ||
``` | ||
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On VCU128, you can now flash this image to the SPI using Vivado: | ||
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```bash | ||
# Define XILINX_PORT, XILINX_HOST, FPGA_PATH to let Vivado find your FPGA | ||
# See defaults in xilinx.mk | ||
make chs-xil-flash BOARD=vcu128 MODE=batch | ||
``` | ||
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## FPGA | ||
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To build the bitstream for FPGA, initialize the repository with `make all` then run `make chs-xil-all` followed by desired arguments: | ||
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* `BOARD=[genesys2,vcu128]`: select supported evaluation board (note `zcu102` is also supported but do not boot Linux as it does not provide access to an SPI flash or an SD card). | ||
* `INT-JTAG=[1,0]`: (only on vcu128) connect the debugger to the intenal JTAG chain (see BSCANE2 primitive) or to an external JTAG dongle (if 0). | ||
* `MODE=[batch,gui]`: open Vivado GUI or execute in shell. | ||
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You can flash the bitstream from the GUI with `make chs-xil-gui` or directly in shell using `make chs-xil-program MODE=batch BOARD=[genesys2,vcu128]`. Here again you will need to define `XILINX_PORT`, `XILINX_HOST`, `FPGA_PATH` for your setup. At IIS, find default values in `carfield.mk`. | ||
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## License | ||
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Unless specified otherwise in the respective file headers, all code checked into this repository is made available under a permissive license. All hardware sources and tool scripts are licensed under the Solderpad Hardware License 0.51 (see `LICENSE`) with the exception of generated register file code (e.g. `hw/regs/*.sv`), which is generated by a fork of lowRISC's [`regtool`](https://github.com/lowRISC/opentitan/blob/master/util/regtool.py) and licensed under Apache 2.0. All software sources are licensed under Apache 2.0. |
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@@ -11,6 +11,9 @@ BENDER ?= bender | |
VLOG_ARGS ?= -suppress 2583 -suppress 13314 | ||
VSIM ?= vsim | ||
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# Define board for FPGA flow and/or device tree selection | ||
BOARD ?= genesys2 | ||
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# Define used paths (prefixed to avoid name conflicts) | ||
CHS_ROOT ?= $(shell $(BENDER) path cheshire) | ||
CHS_REG_DIR := $(shell $(BENDER) path register_interface) | ||
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@@ -51,7 +54,7 @@ chs-clean-deps: | |
###################### | ||
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CHS_NONFREE_REMOTE ?= [email protected]:pulp-restricted/cheshire-nonfree.git | ||
CHS_NONFREE_COMMIT ?= 1c70a67 | ||
CHS_NONFREE_COMMIT ?= d96f3a2 | ||
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chs-nonfree-init: | ||
git clone $(CHS_NONFREE_REMOTE) $(CHS_ROOT)/nonfree | ||
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@@ -150,25 +153,26 @@ CHS_SIM_ALL += $(CHS_ROOT)/target/sim/models/24FC1025.v | |
CHS_SIM_ALL += $(CHS_ROOT)/target/sim/vsim/compile.cheshire_soc.tcl | ||
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############# | ||
# FPGA Flow # | ||
# Emulation # | ||
############# | ||
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$(CHS_ROOT)/target/xilinx/scripts/add_sources.tcl: Bender.yml | ||
$(BENDER) script vivado -t fpga -t cv64a6_imafdcsclic_sv39 -t cva6 > $@ | ||
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CHS_XILINX_ALL += $(CHS_ROOT)/target/xilinx/scripts/add_sources.tcl | ||
include $(CHS_ROOT)/target/xilinx/xilinx.mk | ||
include $(CHS_XIL_DIR)/sim/simulate.mk | ||
CHS_XILINX_ALL += $(CHS_XIL_DIR)/scripts/add_sources.tcl | ||
CHS_LINUX_IMG += $(CHS_SW_DIR)/boot/linux-${BOARD}.gpt.bin | ||
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################################# | ||
# Phonies (KEEP AT END OF FILE) # | ||
################################# | ||
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.PHONY: chs-all chs-nonfree-init chs-clean-deps chs-sw-all chs-hw-all chs-bootrom-all chs-sim-all chs-xilinx-all | ||
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CHS_ALL += $(CHS_SW_ALL) $(CHS_HW_ALL) $(CHS_SIM_ALL) $(CHS_XILINX_ALL) | ||
CHS_ALL += $(CHS_SW_ALL) $(CHS_HW_ALL) $(CHS_SIM_ALL) | ||
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chs-all: $(CHS_ALL) | ||
chs-sw-all: $(CHS_SW_ALL) | ||
chs-hw-all: $(CHS_HW_ALL) | ||
chs-bootrom-all: $(CHS_BOOTROM_ALL) | ||
chs-sim-all: $(CHS_SIM_ALL) | ||
chs-xilinx-all: $(CHS_XILINX_ALL) | ||
chs-linux-img: $(CHS_LINUX_IMG) |
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// Axel Vanoni <[email protected]> | ||
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/dts-v1/; | ||
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/ { | ||
#address-cells = <2>; | ||
#size-cells = <2>; | ||
compatible = "eth,cheshire-dev"; | ||
model = "eth,cheshire"; | ||
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chosen { | ||
stdout-path = "/soc/serial@3002000:115200"; | ||
}; | ||
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@@ -74,22 +76,16 @@ | |
interrupts = <2 3 4 5 6 7 8 9 10 11 12 13 14 15 16>; | ||
reg = <0x0 0x3003000 0x0 0x1000>; | ||
}; | ||
spi@3004000 { | ||
spi: spi@3004000 { | ||
compatible = "opentitan,spi-host", "lowrisc,spi"; | ||
interrupt-parent = <&PLIC0>; | ||
interrupts = <17 18>; | ||
reg = <0x0 0x3004000 0x0 0x1000>; | ||
num-cs = <2>; | ||
clock-frequency = <50000000>; | ||
max-frequency = <25000000>; | ||
#address-cells = <1>; | ||
#size-cells = <0>; | ||
mmc@0 { | ||
compatible = "mmc-spi-slot"; | ||
reg = <0>; | ||
spi-max-frequency = <25000000>; | ||
voltage-ranges = <3300 3300>; | ||
disable-wp; | ||
}; | ||
}; | ||
vga@3007000 { | ||
compatible = "eth,axi-vga"; | ||
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// Copyright 2022 ETH Zurich and University of Bologna. | ||
// Solderpad Hardware License, Version 0.51, see LICENSE for details. | ||
// SPDX-License-Identifier: SHL-0.51 | ||
// | ||
// Cyril Koenig <[email protected]> | ||
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/include/ "cheshire.dtsi" | ||
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&spi { | ||
boot-with = <0>; | ||
mmc@0 { | ||
compatible = "mmc-spi-slot"; | ||
reg = <0>; // CS | ||
spi-max-frequency = <25000000>; | ||
voltage-ranges = <3300 3300>; | ||
disable-wp; | ||
}; | ||
}; |
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@@ -0,0 +1,27 @@ | ||
// Copyright 2022 ETH Zurich and University of Bologna. | ||
// Solderpad Hardware License, Version 0.51, see LICENSE for details. | ||
// SPDX-License-Identifier: SHL-0.51 | ||
// | ||
// Cyril Koenig <[email protected]> | ||
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/include/ "cheshire.dtsi" | ||
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&spi { | ||
boot-with = <1>; | ||
nor@1 { | ||
#address-cells = <0x1>; | ||
#size-cells = <0x1>; | ||
// Note : u-boot does not find mt25qu02g | ||
compatible = "mt25qu02g", "jedec,spi-nor"; | ||
reg = <0x1>; // CS | ||
spi-max-frequency = <25000000>; | ||
spi-rx-bus-width = <0x1>; | ||
spi-tx-bus-width = <0x1>; | ||
disable-wp; | ||
partition@0 { | ||
label = "all"; | ||
reg = <0x0 0x6000000>; // 96 MB | ||
read-only; | ||
}; | ||
}; | ||
}; |
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