fpga: Debug new CI

cheshire.mk

@@ -54,7 +54,7 @@ chs-clean-deps:
 ######################
 
 CHS_NONFREE_REMOTE ?= [email protected]:pulp-restricted/cheshire-nonfree.git
-CHS_NONFREE_COMMIT ?= d96f3a2
+CHS_NONFREE_COMMIT ?= df86b58bfd1ad8f69a7518ea9beebac3595f0d5c
 
 chs-nonfree-init:
 	git clone $(CHS_NONFREE_REMOTE) $(CHS_ROOT)/nonfree

target/xilinx/scripts/program.tcl

@@ -3,7 +3,6 @@
 # SPDX-License-Identifier: SHL-0.51
 #
 # Author: Florian Zaruba <[email protected]>
-# Description: Program Genesys II
 
 open_hw_manager
 
@@ -17,6 +16,8 @@ if {$::env(BOARD) eq "vcu128"} {
   set hw_device [get_hw_devices xcvu37p_0]
 }
 
+set_property PARAM.FREQUENCY 15000000 [get_hw_targets *]
+
 current_hw_device $hw_device
 set_property PROGRAM.FILE $::env(BIT) $hw_device
 program_hw_devices $hw_device

target/xilinx/scripts/run.tcl

@@ -115,9 +115,11 @@ if {[info exists ::env(CHECK_TIMING)] && $::env(CHECK_TIMING)==1} {
 }
 
 # Output Verilog netlist + SDC for timing simulation
-write_verilog -force -mode funcsim out/${project}_funcsim.v
-write_verilog -force -mode timesim out/${project}_timesim.v
-# write_sdf     -force out/${project}_timesim.sdf
+if {[info exists ::env(EXPORT_SDF)] && $::env(EXPORT_SDF)==1} {
+  write_verilog -force -mode funcsim out/${project}_funcsim.v
+  write_verilog -force -mode timesim out/${project}_timesim.v
+  write_sdf     -force out/${project}_timesim.sdf
+}
 
 # Reports
 exec mkdir -p reports/

target/xilinx/xilinx.mk

@@ -78,7 +78,7 @@ $(bit): $(ips) $(CHS_XIL_DIR)/scripts/add_sources.tcl
 	cd $(CHS_XIL_DIR) && $(VIVADOENV) $(VIVADO) $(VIVADOFLAGS) -source scripts/prologue.tcl -source scripts/run.tcl
 	cp $(CHS_XIL_DIR)/$(PROJECT).runs/impl_1/*.bit $(out)
 	cp $(CHS_XIL_DIR)/$(PROJECT).runs/impl_1/*.ltx $(out)
-	cp $(CHS_XIL_DIR)/$(PROJECT).runs/impl_1/*.dcp $(out)
+	cp $(CHS_XIL_DIR)/$(PROJECT).runs/impl_1/*_routed.dcp $(out)
 
 # Generate ips
 %.xci: