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hw: Simplify UNBENT integration, some cleanup (#69)
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* hw: Simplify UNBENT integration, clean up parameterization

* hw: Add UNBENT feature reg, reg cleanup
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@paulsc96
paulsc96 authored Sep 5, 2023
1 parent 91ea189 commit 6308a81
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Showing 9 changed files with 251 additions and 265 deletions.
4 changes: 2 additions & 2 deletions hw/bootrom/cheshire_bootrom.S
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Original file line number Diff line number Diff line change
Expand Up @@ -58,7 +58,7 @@ _start:

// If LLC present: Wait for end of BIST, then extend stack and set to all SPM
la t0, __base_regs
lw t0, 76(t0) // regs.HW_FEATURES
lw t0, 80(t0) // regs.HW_FEATURES
andi t0, t0, 2 // regs.HW_FEATURES.llc
beqz t0, _prom_check_run
la t0, __base_llc
Expand All @@ -73,7 +73,7 @@ _wait_llc_bist:
// Correct stack to start at end of SPM
la t0, __base_regs
la sp, __base_spm
lw t0, 80(t0) // regs.LLC_SIZE
lw t0, 84(t0) // regs.LLC_SIZE
add sp, sp, t0
addi sp, sp, -8

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8 changes: 4 additions & 4 deletions hw/bootrom/cheshire_bootrom.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -54,7 +54,7 @@ module cheshire_bootrom #(
022: data_o = 32'h0297ada1 /* 0x0058 */;
023: data_o = 32'h82930100 /* 0x005c */;
024: data_o = 32'ha283fa62 /* 0x0060 */;
025: data_o = 32'hf29304c2 /* 0x0064 */;
025: data_o = 32'hf2930502 /* 0x0064 */;
026: data_o = 32'h8e630022 /* 0x0068 */;
027: data_o = 32'h12970202 /* 0x006c */;
028: data_o = 32'h82930100 /* 0x0070 */;
Expand All @@ -69,7 +69,7 @@ module cheshire_bootrom #(
037: data_o = 32'h0117f722 /* 0x0094 */;
038: data_o = 32'h01130e00 /* 0x0098 */;
039: data_o = 32'ha283f6a1 /* 0x009c */;
040: data_o = 32'h91160502 /* 0x00a0 */;
040: data_o = 32'h91160542 /* 0x00a0 */;
041: data_o = 32'h02971161 /* 0x00a4 */;
042: data_o = 32'h82930100 /* 0x00a8 */;
043: data_o = 32'ha283f5a2 /* 0x00ac */;
Expand All @@ -85,7 +85,7 @@ module cheshire_bootrom #(
053: data_o = 32'h0397f322 /* 0x00d4 */;
054: data_o = 32'h83930100 /* 0x00d8 */;
055: data_o = 32'ha383f2a3 /* 0x00dc */;
056: data_o = 32'h038a0583 /* 0x00e0 */;
056: data_o = 32'h038a04c3 /* 0x00e0 */;
057: data_o = 32'h43059396 /* 0x00e4 */;
058: data_o = 32'h0062a023 /* 0x00e8 */;
059: data_o = 32'hcce30291 /* 0x00ec */;
Expand All @@ -101,7 +101,7 @@ module cheshire_bootrom #(
069: data_o = 32'h03970003 /* 0x0114 */;
070: data_o = 32'h83930100 /* 0x0118 */;
071: data_o = 32'ha383eea3 /* 0x011c */;
072: data_o = 32'h038a0583 /* 0x0120 */;
072: data_o = 32'h038a04c3 /* 0x0120 */;
073: data_o = 32'ha3039396 /* 0x0124 */;
074: data_o = 32'h1ee30002 /* 0x0128 */;
075: data_o = 32'h0291fe03 /* 0x012c */;
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73 changes: 49 additions & 24 deletions hw/cheshire_pkg.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -19,6 +19,12 @@ package cheshire_pkg;
return (width != 32'd0) ? unsigned'(width-1) : 32'd0;
endfunction

// Parameterization constants
localparam int unsigned MaxCoresWidth = 5;
localparam int unsigned MaxExtAxiMstWidth = 4;
localparam int unsigned MaxExtAxiSlvWidth = 4;
localparam int unsigned MaxExtRegSlvWidth = 4;

// Parameters defined by generated hardware (regenerate to adapt)
localparam int unsigned SpihNumCs = spi_host_reg_pkg::NumCS - 1; // Last CS is dummy
localparam int unsigned SlinkNumChan = serial_link_single_channel_reg_pkg::NumChannels;
Expand Down Expand Up @@ -67,7 +73,7 @@ package cheshire_pkg;
doub_bt Cva6ExtCieLength;
bit Cva6ExtCieOnTop;
// Hart parameters
bit [3:0] NumCores;
bit [MaxCoresWidth-1:0] NumCores;
doub_bt NumExtIrqHarts;
doub_bt NumExtDbgHarts;
dw_bt Core1UserAmoBit;
Expand Down Expand Up @@ -97,19 +103,19 @@ package cheshire_pkg;
dw_bt RegMaxWriteTxns;
aw_bt RegAmoNumCuts;
bit RegAmoPostCut;
// External AXI ports (at most 8 ports and rules)
bit [2:0] AxiExtNumMst;
bit [3:0] AxiExtNumSlv;
bit [3:0] AxiExtNumRules;
byte_bt [15:0] AxiExtRegionIdx;
doub_bt [15:0] AxiExtRegionStart;
doub_bt [15:0] AxiExtRegionEnd;
// External reg slaves (at most 8 ports and rules)
bit [2:0] RegExtNumSlv;
bit [2:0] RegExtNumRules;
byte_bt [7:0] RegExtRegionIdx;
doub_bt [7:0] RegExtRegionStart;
doub_bt [7:0] RegExtRegionEnd;
// External AXI ports (limited number of ports and rules)
bit [MaxExtAxiMstWidth-1:0] AxiExtNumMst;
bit [MaxExtAxiSlvWidth-1:0] AxiExtNumSlv;
bit [MaxExtAxiSlvWidth-1:0] AxiExtNumRules;
byte_bt [2**MaxExtAxiSlvWidth-1:0] AxiExtRegionIdx;
doub_bt [2**MaxExtAxiSlvWidth-1:0] AxiExtRegionStart;
doub_bt [2**MaxExtAxiSlvWidth-1:0] AxiExtRegionEnd;
// External reg slaves (limited number of ports and rules)
bit [MaxExtRegSlvWidth-1:0] RegExtNumSlv;
bit [MaxExtRegSlvWidth-1:0] RegExtNumRules;
byte_bt [2**MaxExtRegSlvWidth-1:0] RegExtRegionIdx;
doub_bt [2**MaxExtRegSlvWidth-1:0] RegExtRegionStart;
doub_bt [2**MaxExtRegSlvWidth-1:0] RegExtRegionEnd;
// Real-time clock speed
word_bt RtcFreq;
// Address of platform ROM
Expand Down Expand Up @@ -177,9 +183,21 @@ package cheshire_pkg;
// Interrupts //
//////////////////

// Bus Error interrupts
typedef struct packed {
logic r;
logic w;
} axi_err_intr_t;

typedef struct packed {
axi_err_intr_t cores;
axi_err_intr_t dma;
axi_err_intr_t vga;
} cheshire_bus_err_intr_t;

// Defined interrupts
typedef struct packed {
logic [5:0] bus_err; // VGA, DMA, CVA6
cheshire_bus_err_intr_t bus_err;
logic [31:0] gpio;
logic spih_spi_event;
logic spih_error;
Expand Down Expand Up @@ -234,21 +252,28 @@ package cheshire_pkg;
return cfg.LlcSetAssoc * cfg.LlcNumLines * cfg.LlcNumBlocks * cfg.AxiDataWidth / 8;
endfunction

// Static addresses
// Static addresses (defined here only if multiply used)
localparam doub_bt AmDbg = 'h0000_0000; // Base of AXI peripherals
localparam doub_bt AmBrom = 'h0200_0000; // Base of reg peripherals
localparam doub_bt AmRegs = 'h0300_0000;
localparam doub_bt AmLlc = 'h0300_1000;
localparam doub_bt AmSlink = 'h0300_6000;
localparam doub_bt AmBusErr = 'h0300_9000;
localparam doub_bt AmSpm = 'h1000_0000; // Cached region at bottom, uncached on top
localparam doub_bt AmClic = 'h0800_0000;

// Static masks
localparam doub_bt AmSpmBaseUncached = 'h1400_0000;
localparam doub_bt AmSpmRegionMask = 'h03FF_FFFF;

// Reg bus error unit indices
localparam int unsigned RegBusErrVga = 0;
localparam int unsigned RegBusErrDma = 1;
localparam int unsigned RegBusErrCoresBase = 2;

// AXI Xbar master indices
typedef struct packed {
aw_bt [15:0] cores;
aw_bt [2**MaxCoresWidth-1:0] cores;
aw_bt dbg;
aw_bt dma;
aw_bt slink;
Expand Down Expand Up @@ -347,9 +372,9 @@ package cheshire_pkg;
aw_bt slink;
aw_bt vga;
aw_bt axirt;
aw_bt [15:0] clic;
aw_bt irq_router;
aw_bt bus_err;
aw_bt [2**MaxCoresWidth-1:0] bus_err;
aw_bt [2**MaxCoresWidth-1:0] clic;
aw_bt ext_base;
aw_bt num_out;
aw_bt num_rules;
Expand All @@ -371,12 +396,12 @@ package cheshire_pkg;
if (cfg.SerialLink) begin i++; ret.slink = i; r++; ret.map[r] = '{i, AmSlink, AmSlink +'h1000}; end
if (cfg.Vga) begin i++; ret.vga = i; r++; ret.map[r] = '{i, 'h0300_7000, 'h0300_8000}; end
if (cfg.AxiRt) begin i++; ret.axirt = i; r++; ret.map[r] = '{i, 'h0300_8000, 'h0300_9000}; end
if (cfg.BusErr) begin i++; ret.bus_err = i; r++; ret.map[r] = '{i, 'h0300_9000, 'h0300_a000}; end
if (cfg.IrqRouter) begin i++; ret.irq_router = i; r++; ret.map[r] = '{i, 'h0208_0000, 'h020c_0000}; end
if (cfg.Clic) begin
for (int j = 0; j < cfg.NumCores; j++) begin
i++; ret.clic[j] = i; r++; ret.map[r] = '{i, 'h0800_0000 + j * 'h4_0000, 'h0800_0000 + (j + 1) * 'h4_0000};
end
if (cfg.Clic) for (int j = 0; j < cfg.NumCores; j++) begin
i++; ret.clic[j] = i; r++; ret.map[r] = '{i, AmClic + j*'h40000, AmClic + (j+1)*'h40000};
end
if (cfg.BusErr) for (int j = 0; j < 2 + cfg.NumCores; j++) begin
i++; ret.bus_err[j] = i; r++; ret.map[r] = '{i, AmBusErr + j*'h40, AmBusErr + (j+1)*'h40};
end
i++; r++;
ret.ext_base = i;
Expand Down
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