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Add VCS simulation flow #163

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Add VCS simulation flow #163

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CyrilKoe
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@CyrilKoe CyrilKoe commented Oct 29, 2024

This required two changes:
AXI : pulp-platform/axi@6879518
iDMA: pulp-platform/iDMA@1af5451

  • cheshire_pkg.sv
    • VCS: Support for parameter of type 'DefaultMapEntry' inside 'Function' is not yet implemented
  • vip_cheshire_soc.sv
    • @(negedge rst_n) is not detected by VCS as rst_n is de-asserted at delta 0.
    • streams require explicit cast to string
    • concatenation of interfaces using { } is not in the standard
    • removed logic for gate level (see example module tri_latch page 857 of IEEE Std 1800™-2023)

>  The following expression is illegally connected to a gate.
>  Variables cannot be connected to the output of gates with driving strength.
>  Expression: spih_sd_i[0] of type: logic
>  Please refer to section "Gate and switch level modeling" in IEEE standards
>  1364 (Verilog) or 1800 (SystemVerilog).
> VCS: Support for parameter of type 'DefaultMapEntry' inside 'Function' is not yet
> implemented
@CyrilKoe CyrilKoe force-pushed the ck/vcs branch 2 times, most recently from b5aa77d to 16451dd Compare October 29, 2024 16:17
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