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Add VCS simulation flow #163

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Add VCS simulation flow #163

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Commits on Oct 25, 2024

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Commits on Oct 29, 2024

  1. vip: Don't use lofic for gate modeling

    >  The following expression is illegally connected to a gate.
    >  Variables cannot be connected to the output of gates with driving strength.
    >  Expression: spih_sd_i[0] of type: logic
    >  Please refer to section "Gate and switch level modeling" in IEEE standards
    >  1364 (Verilog) or 1800 (SystemVerilog).
    CyrilKoe committed Oct 29, 2024
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  2. cheshire_pkg: Replace parameter by variables inside function

    > VCS: Support for parameter of type 'DefaultMapEntry' inside 'Function' is not yet
    > implemented
    CyrilKoe committed Oct 29, 2024
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  4. idma: Bump hash for VCS

    CyrilKoe committed Oct 29, 2024
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  6. vip: Questa fix

    CyrilKoe committed Oct 29, 2024
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  8. ci: Add vcs to CI

    CyrilKoe committed Oct 29, 2024
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