Std cache TB: add bootrom to bender sources

Bender.yml

@@ -307,6 +307,7 @@ sources:
           - corev_apu/tb/tb_std_cache_subsystem/hdl/icache_intf.sv
           - corev_apu/tb/tb_std_cache_subsystem/hdl/sram_intf.sv
           - corev_apu/tb/tb_std_cache_subsystem/hdl/cva6_cache_dummy.sv
+          - corev_apu/bootrom/bootrom.sv
 
     # TODO target define FPGA target + verification etc
     #   - target: test