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Added 32/64 to RVTEST_CASE for Zicond tests #424

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merged 2 commits into from
Jan 19, 2024

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davidharrishmc
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@davidharrishmc davidharrishmc commented Jan 12, 2024

Description

Added 32/64 to RVTEST_CASE for Zicond tests so riscof selects the appropriate tests for the appropriate architectures.

Related Issues

N/A

Ratified/Unratified Extensions

  • [x ] Ratified
  • Unratified

List Extensions

Zicond

Reference Model Used

  • [x ] SAIL
  • [ x] Spike
  • Other - < SPECIFY HERE >

Mandatory Checklist:

  • [ x] All tests are compliant with the test-format spec present in this repo ?
  • [ x] Ran the new tests on RISCOF with SAIL/Spike as reference model successfully ?
  • Ran the new tests on RISCOF in coverage mode
  • Link to Google-Drive folder containing the new coverage reports (See this for more info): < SPECIFY HERE >
  • Link to PR in RISCV-ISAC from which the reports were generated : < SPECIFY HERE >
  • [ x] Changelog entry created with a minor patch

Optional Checklist:

  • RISCV-V CTG PR link if tests were generated using it : < SPECIFY HERE >
  • Were the tests hand-written/modified ?
  • Have you run these on any hard DUT model ? Please specify name and provide link if possible in the description
  • If you have modified arch_test.h Please provide a detailed description of the changes in the Description section above.

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@allenjbaum allenjbaum left a comment

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This adds back explicit widths which otherwise will fail

@allenjbaum allenjbaum merged commit 8a52b01 into riscv-non-isa:main Jan 19, 2024
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2 participants