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Added 32/64 to RVTEST_CASE for Zicond tests #424

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merged 2 commits into from
Jan 19, 2024
Merged

Added 32/64 to RVTEST_CASE for Zicond tests #424

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88b8c79
Added 32/64 to RVTEST_CASE for Zicond tests
davidharrishmc Jan 12, 2024
bcc4b46
Synced changes in CHANGELOG
davidharrishmc Jan 17, 2024
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7 changes: 5 additions & 2 deletions CHANGELOG.md
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Original file line number Diff line number Diff line change
@@ -1,16 +1,19 @@
# CHANGELOG

## [3.8.9] -- 2024-01-12
- Fixed Check ISA fields to include 32/64 in Zicond tests. Note that the riscv-ctg CGFs have not been updated.

## [3.8.8] -- 2024-01-04
- Fixed macros to allow assembling tests with LLVM.

## [3.8.7] -- 2024-01-02
- Update satp initialization macro

## [3.8.6] -- 2013-12-24
## [3.8.6] -- 2023-12-24
- Fixed check ISA fields to include 32/64 in Zca and CMO tests. Note that the riscv-ctg CGFs have not been updated.
- Fixed check ISA fields in rv32e_m/B/src/ror-01 and rori-01 that listed I instead of E. Again, CGF has not been updated.

## [3.8.5] -- 2013-12-23
## [3.8.5] -- 2023-12-23
- Renamed rv32e_unratified to rv32e_m because the E extension has been ratified January 2023
- Copied missing ebreak.S and ecall.S tests from rv32i_m/privilege to rv32e_m/privilege and update ISA for E

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2 changes: 1 addition & 1 deletion riscv-test-suite/rv32i_m/Zicond/src/czero.eqz-01.S
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Expand Up @@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*Zicond.*);def TEST_CASE_1=True;",czero.eqz)
RVTEST_CASE(0,"//check ISA:=regex(.*32.*Zicond.*);def TEST_CASE_1=True;",czero.eqz)

RVTEST_SIGBASE(x1,signature_x1_1)

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2 changes: 1 addition & 1 deletion riscv-test-suite/rv32i_m/Zicond/src/czero.nez-01.S
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Expand Up @@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*Zicond.*);def TEST_CASE_1=True;",czero.nez)
RVTEST_CASE(0,"//check ISA:=regex(.*32.*Zicond.*);def TEST_CASE_1=True;",czero.nez)

RVTEST_SIGBASE(x1,signature_x1_1)

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2 changes: 1 addition & 1 deletion riscv-test-suite/rv64i_m/Zicond/src/czero.eqz-01.S
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Expand Up @@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*Zicond.*);def TEST_CASE_1=True;",czero.eqz)
RVTEST_CASE(0,"//check ISA:=regex(.*64.*Zicond.*);def TEST_CASE_1=True;",czero.eqz)

RVTEST_SIGBASE(x1,signature_x1_1)

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2 changes: 1 addition & 1 deletion riscv-test-suite/rv64i_m/Zicond/src/czero.nez-01.S
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Original file line number Diff line number Diff line change
Expand Up @@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*Zicond.*);def TEST_CASE_1=True;",czero.nez)
RVTEST_CASE(0,"//check ISA:=regex(.*64.*Zicond.*);def TEST_CASE_1=True;",czero.nez)

RVTEST_SIGBASE(x1,signature_x1_1)

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