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Hexagon adapter and small additions #22

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merged 23 commits into from
Apr 10, 2024
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@Rot127 Rot127 commented Oct 27, 2023

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@Rot127 Rot127 marked this pull request as ready for review November 13, 2023 19:45
This is necessary if architectures need the context they
are embedded in.
Context means: Instruction word +- x bytes.
For Hexagon the disassembly and IL steps are incorrect,
if the context is not the same every time and differs
from the actual binary.
Because instructions disassemble differently depending on
their neighbors.
If the neighbor instruction of a packet indicated the
start of it, and during the IL step execution this
neighboring instructions is no longer the same,
the interpretation is different and the IL step is invalid.
If the sf bytes contain a '\0' byte, the code.size() call later
returned the wrong size. Hence we directly read it as ut8 *
If the post-operand list had a register twice in it and
the last entry had the correct value, a mismatch
happened anyway.
Because the first value was tested and did not match.

This is not correct, since multiple writes to a register can happen.
Only the last post-operand should be considered.
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Rot127 commented Mar 16, 2024

@thestr4ng3r Please take a quick look and merge if ok. Personally I wouldn't squash it. But if you prefer it, let me know please.

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Rot127 commented Apr 10, 2024

ping

@thestr4ng3r thestr4ng3r merged commit a0a023e into rizinorg:master Apr 10, 2024
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@Rot127 Rot127 deleted the hexagon branch April 10, 2024 14:29
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4 participants