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Merge pull request #400 from slaclab/pre-release
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v1.9.8 release candidate
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@ruck314
ruck314 authored Mar 20, 2019
2 parents aab96e9 + 456eaec commit 8c50179
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Showing 121 changed files with 5,919 additions and 1,510 deletions.
320 changes: 193 additions & 127 deletions axi/axi-lite/rtl/AxiDualPortRam.vhd
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3 changes: 0 additions & 3 deletions axi/axi-lite/tb/AxiLiteAsyncTb.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -101,9 +101,6 @@ begin
U_AxiDualPortRam_1 : entity work.AxiDualPortRam
generic map (
TPD_G => TPD_G,
BRAM_EN_G => true,
REG_EN_G => true,
-- MODE_G => MODE_G,
AXI_WR_EN_G => true,
SYS_WR_EN_G => false,
SYS_BYTE_WR_EN_G => false,
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2 changes: 0 additions & 2 deletions axi/axi-lite/tb/AxiLiteWriteFilterTb.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -131,8 +131,6 @@ begin
U_Mem : entity work.AxiDualPortRam
generic map (
TPD_G => TPD_G,
BRAM_EN_G => true,
REG_EN_G => true,
AXI_WR_EN_G => true,
SYS_WR_EN_G => false,
COMMON_CLK_G => false,
Expand Down
30 changes: 18 additions & 12 deletions axi/dma/rtl/AxiStreamDmaRingWrite.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -257,8 +257,9 @@ begin
U_AxiDualPortRam_Start : entity work.AxiDualPortRam
generic map (
TPD_G => TPD_G,
BRAM_EN_G => false,
REG_EN_G => false,
SYNTH_MODE_G => "inferred",
MEMORY_TYPE_G=> "distributed",
READ_LATENCY_G => 0,
AXI_WR_EN_G => true,
SYS_WR_EN_G => false,
ADDR_WIDTH_G => RAM_ADDR_WIDTH_C,
Expand All @@ -279,8 +280,9 @@ begin
U_AxiDualPortRam_End : entity work.AxiDualPortRam
generic map (
TPD_G => TPD_G,
BRAM_EN_G => false,
REG_EN_G => false,
SYNTH_MODE_G => "inferred",
MEMORY_TYPE_G=> "distributed",
READ_LATENCY_G => 0,
AXI_WR_EN_G => true,
SYS_WR_EN_G => false,
ADDR_WIDTH_G => RAM_ADDR_WIDTH_C,
Expand All @@ -302,8 +304,9 @@ begin
U_AxiDualPortRam_Next : entity work.AxiDualPortRam
generic map (
TPD_G => TPD_G,
BRAM_EN_G => false,
REG_EN_G => false,
SYNTH_MODE_G => "inferred",
MEMORY_TYPE_G=> "distributed",
READ_LATENCY_G => 0,
AXI_WR_EN_G => false,
SYS_WR_EN_G => true,
ADDR_WIDTH_G => RAM_ADDR_WIDTH_C,
Expand All @@ -325,8 +328,9 @@ begin
U_AxiDualPortRam_Trigger : entity work.AxiDualPortRam
generic map (
TPD_G => TPD_G,
BRAM_EN_G => false,
REG_EN_G => false,
SYNTH_MODE_G => "inferred",
MEMORY_TYPE_G=> "distributed",
READ_LATENCY_G => 0,
AXI_WR_EN_G => false,
SYS_WR_EN_G => true,
ADDR_WIDTH_G => RAM_ADDR_WIDTH_C,
Expand All @@ -349,8 +353,9 @@ begin
U_AxiDualPortRam_Mode : entity work.AxiDualPortRam
generic map (
TPD_G => TPD_G,
BRAM_EN_G => false,
REG_EN_G => false,
SYNTH_MODE_G => "inferred",
MEMORY_TYPE_G=> "distributed",
READ_LATENCY_G => 0,
AXI_WR_EN_G => true,
SYS_WR_EN_G => false,
COMMON_CLK_G => false,
Expand All @@ -375,8 +380,9 @@ begin
U_AxiDualPortRam_Status : entity work.AxiDualPortRam
generic map (
TPD_G => TPD_G,
BRAM_EN_G => false,
REG_EN_G => false,
SYNTH_MODE_G => "inferred",
MEMORY_TYPE_G=> "distributed",
READ_LATENCY_G => 0,
AXI_WR_EN_G => false,
SYS_WR_EN_G => true,
ADDR_WIDTH_G => RAM_ADDR_WIDTH_C,
Expand Down
2 changes: 0 additions & 2 deletions axi/dma/rtl/AxiStreamDmaV2Desc.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -361,8 +361,6 @@ begin
U_AddrRam : entity work.AxiDualPortRam
generic map (
TPD_G => TPD_G,
REG_EN_G => true,
BRAM_EN_G => true,
COMMON_CLK_G => true,
ADDR_WIDTH_G => DESC_AWIDTH_G,
DATA_WIDTH_G => 32)
Expand Down
3 changes: 2 additions & 1 deletion axi/dma/rtl/AxiStreamDmaWrite.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -33,6 +33,7 @@ entity AxiStreamDmaWrite is
AXI_CONFIG_G : AxiConfigType := AXI_CONFIG_INIT_C;
AXI_BURST_G : slv(1 downto 0) := "01";
AXI_CACHE_G : slv(3 downto 0) := "1111";
BURST_BYTES_G : positive range 1 to 4096 := 4096;
SW_CACHE_EN_G : boolean := false;
ACK_WAIT_BVALID_G : boolean := true;
PIPE_STAGES_G : natural := 1;
Expand Down Expand Up @@ -68,7 +69,7 @@ architecture rtl of AxiStreamDmaWrite is

constant DATA_BYTES_C : integer := LOC_AXIS_CONFIG_C.TDATA_BYTES_C;
constant ADDR_LSB_C : integer := bitSize(DATA_BYTES_C-1);
constant AWLEN_C : slv(7 downto 0) := getAxiLen(AXI_CONFIG_G, 4096);
constant AWLEN_C : slv(7 downto 0) := getAxiLen(AXI_CONFIG_G, BURST_BYTES_G);
constant FIFO_ADDR_WIDTH_C : natural := ite((AXI_CONFIG_G.LEN_BITS_C<3),4,(AXI_CONFIG_G.LEN_BITS_C+1));

type StateType is (
Expand Down
18 changes: 10 additions & 8 deletions axi/simlink/src/RogueTcpMemory.c
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Original file line number Diff line number Diff line change
Expand Up @@ -259,9 +259,9 @@ void RogueTcpMemoryUpdate ( void *userPtr ) {
if ( getInt(s_reset) == 1 ) {
data->state = ST_IDLE;
setInt(s_arvalid,0);
setInt(s_rready,0);
setInt(s_rready,1);
setInt(s_awvalid,0);
setInt(s_bready,0);
setInt(s_bready,1);
}

// Data movement
Expand Down Expand Up @@ -306,7 +306,7 @@ void RogueTcpMemoryUpdate ( void *userPtr ) {
setInt(s_araddr,(data->addr+data->curr));
setInt(s_arprot,0);
setInt(s_arvalid,1);
setInt(s_arready,0);
setInt(s_rready,1);
data->state = ST_RADDR;
}
break;
Expand All @@ -318,7 +318,7 @@ void RogueTcpMemoryUpdate ( void *userPtr ) {
if ( getInt(s_wready) ) setInt(s_wvalid,0);

if ( getInt(s_bvalid) ) {
setInt(s_bready,0);
//setInt(s_bready,0);
data->result = getInt(s_bresp);

if (data->curr == data->size) {
Expand Down Expand Up @@ -348,7 +348,7 @@ void RogueTcpMemoryUpdate ( void *userPtr ) {
data->data[data->curr++] = (data32 >> 16) & 0xFF;
data->data[data->curr++] = (data32 >> 24) & 0xFF;

setInt(s_rready,0);
//setInt(s_rready,0);

if (data->curr == data->size) {
RogueTcpMemorySend(data,portData); // state goes to idle
Expand All @@ -357,10 +357,12 @@ void RogueTcpMemoryUpdate ( void *userPtr ) {
}
break;

// One clock idle
// Wait for RVALID and BVALID to fall
case ST_PAUSE:
data->state = ST_START;
break;
if ( getInt(s_rvalid) == 0 && getInt(s_bvalid) == 0 ) {
data->state = ST_START;
break;
}
}
}
}
Expand Down
4 changes: 2 additions & 2 deletions base/fifo/ruckus.tcl
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Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,7 @@
source -quiet $::env(RUCKUS_DIR)/vivado_proc.tcl

# Load Source Code
loadSource -dir "$::DIR_PATH/rtl/"
loadSource -dir "$::DIR_PATH/rtl"

# Load Simulation
loadSource -sim_only -dir "$::DIR_PATH/tb/"
loadSource -sim_only -dir "$::DIR_PATH/tb"
4 changes: 2 additions & 2 deletions base/general/ruckus.tcl
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Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,7 @@
source -quiet $::env(RUCKUS_DIR)/vivado_proc.tcl

# Load Source Code
loadSource -dir "$::DIR_PATH/rtl/"
loadSource -dir "$::DIR_PATH/rtl"

# Load Simulation
loadSource -sim_only -dir "$::DIR_PATH/tb/"
loadSource -sim_only -dir "$::DIR_PATH/tb"
2 changes: 1 addition & 1 deletion base/ram/xilinx/SimpleDualPortRamAlteraMfDummy.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -26,7 +26,7 @@ entity SimpleDualPortRamAlteraMf is
COMMON_CLK_G : boolean := false;
RST_POLARITY_G : sl := '1'; -- '1' for active high rst, '0' for active low
MEMORY_TYPE_G : string := "block";
READ_LATENCY_G : natural range 0 to 2 := 1;
READ_LATENCY_G : natural range 0 to 100 := 1;
DATA_WIDTH_G : integer range 1 to (2**24) := 16;
BYTE_WR_EN_G : boolean := false;
BYTE_WIDTH_G : integer range 8 to 9 := 8; -- If BRAM, should be multiple or 8 or 9
Expand Down
6 changes: 3 additions & 3 deletions base/ram/xilinx/SimpleDualPortRamXpm.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,7 @@
-- File : SimpleDualPortRamXpm.vhd
-- Company : SLAC National Accelerator Laboratory
-------------------------------------------------------------------------------
-- Description: Wrapper for XPM Simple Dual Port RAM
-- Description: Wrapper for XPM True Dual Port RAM
-------------------------------------------------------------------------------
-- This file is part of 'SLAC Firmware Standard Library'.
-- It is subject to the license terms in the LICENSE.txt file found in the
Expand All @@ -29,7 +29,7 @@ entity SimpleDualPortRamXpm is
COMMON_CLK_G : boolean := false;
RST_POLARITY_G : sl := '1'; -- '1' for active high rst, '0' for active low
MEMORY_TYPE_G : string := "block";
READ_LATENCY_G : natural range 0 to 2 := 1;
READ_LATENCY_G : natural range 0 to 100 := 1;
DATA_WIDTH_G : integer range 1 to (2**24) := 16;
BYTE_WR_EN_G : boolean := false;
BYTE_WIDTH_G : integer range 8 to 9 := 8; -- If BRAM, should be multiple or 8 or 9
Expand Down Expand Up @@ -74,7 +74,7 @@ begin
USE_MEM_INIT => 1, -- Default value = 1
WAKEUP_TIME => "disable_sleep", -- "disable_sleep" to disable dynamic power saving option
WRITE_DATA_WIDTH_A => DATA_WIDTH_G,
WRITE_MODE_B => ite(READ_LATENCY_G = 0, "read_first", "no_change")) -- Default value = no_change
WRITE_MODE_B => ite(READ_LATENCY_G = 0, "read_first", ite(MEMORY_TYPE_G="block","no_change","read_first"))) -- Default value = no_change
port map (
-- Write Interface
ena => ena,
Expand Down
122 changes: 122 additions & 0 deletions base/ram/xilinx/TrueDualPortRamXpm.vhd
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Original file line number Diff line number Diff line change
@@ -0,0 +1,122 @@
-------------------------------------------------------------------------------
-- File : TrueDualPortRamXpm.vhd
-- Company : SLAC National Accelerator Laboratory
-------------------------------------------------------------------------------
-- Description: Wrapper for XPM True Dual Port RAM
-------------------------------------------------------------------------------
-- This file is part of 'SLAC Firmware Standard Library'.
-- It is subject to the license terms in the LICENSE.txt file found in the
-- top-level directory of this distribution and at:
-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
-- No part of 'SLAC Firmware Standard Library', including this file,
-- may be copied, modified, propagated, or distributed except according to
-- the terms contained in the LICENSE.txt file.
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

use work.StdRtlPkg.all;

library xpm;
use xpm.vcomponents.all;

entity TrueDualPortRamXpm is
generic (
TPD_G : time := 1 ns;
COMMON_CLK_G : boolean := false;
RST_POLARITY_G : sl := '1'; -- '1' for active high rst, '0' for active low
MEMORY_TYPE_G : string := "block";
READ_LATENCY_G : natural range 0 to 100 := 1;
DATA_WIDTH_G : integer range 1 to (2**24) := 16;
BYTE_WR_EN_G : boolean := false;
BYTE_WIDTH_G : integer range 8 to 9 := 8; -- If BRAM, should be multiple or 8 or 9
ADDR_WIDTH_G : integer range 1 to (2**24) := 4);
port (
-- Port A
clka : in sl := '0';
ena : in sl := '1';
wea : in slv(ite(BYTE_WR_EN_G, wordCount(DATA_WIDTH_G, BYTE_WIDTH_G), 1)-1 downto 0) := (others => '0');
regcea : in sl := '1';
rsta : in sl := not(RST_POLARITY_G);
addra : in slv(ADDR_WIDTH_G-1 downto 0) := (others => '0');
dina : in slv(DATA_WIDTH_G-1 downto 0) := (others => '0');
douta : out slv(DATA_WIDTH_G-1 downto 0);
-- Port B
clkb : in sl := '0';
enb : in sl := '1';
web : in slv(ite(BYTE_WR_EN_G, wordCount(DATA_WIDTH_G, BYTE_WIDTH_G), 1)-1 downto 0) := (others => '0');
regceb : in sl := '1';
rstb : in sl := not(RST_POLARITY_G);
addrb : in slv(ADDR_WIDTH_G-1 downto 0) := (others => '0');
dinb : in slv(DATA_WIDTH_G-1 downto 0) := (others => '0');
doutb : out slv(DATA_WIDTH_G-1 downto 0) := (others => '0'));
end TrueDualPortRamXpm;

architecture rtl of TrueDualPortRamXpm is

signal resetA : sl;
signal resetB : sl;

begin

U_RAM : xpm_memory_tdpram
generic map (
ADDR_WIDTH_A => ADDR_WIDTH_G,
ADDR_WIDTH_B => ADDR_WIDTH_G,
AUTO_SLEEP_TIME => 0, -- 0 - Disable auto-sleep feature
BYTE_WRITE_WIDTH_A => ite(BYTE_WR_EN_G, BYTE_WIDTH_G, DATA_WIDTH_G),
BYTE_WRITE_WIDTH_B => ite(BYTE_WR_EN_G, BYTE_WIDTH_G, DATA_WIDTH_G),
CLOCKING_MODE => ite(COMMON_CLK_G, "common_clock", "independent_clock"),
ECC_MODE => "no_ecc", -- Default value = no_ecc
MEMORY_OPTIMIZATION => "true", -- Default value = true
MEMORY_PRIMITIVE => MEMORY_TYPE_G,
MEMORY_SIZE => (DATA_WIDTH_G*(2**ADDR_WIDTH_G)),
MESSAGE_CONTROL => 0, -- Default value = 0
READ_DATA_WIDTH_A => DATA_WIDTH_G,
READ_DATA_WIDTH_B => DATA_WIDTH_G,
READ_LATENCY_A => READ_LATENCY_G,
READ_LATENCY_B => READ_LATENCY_G,
USE_EMBEDDED_CONSTRAINT => 0, -- Default value = 0
USE_MEM_INIT => 1, -- Default value = 1
WAKEUP_TIME => "disable_sleep", -- "disable_sleep" to disable dynamic power saving option
WRITE_DATA_WIDTH_A => DATA_WIDTH_G,
WRITE_DATA_WIDTH_B => DATA_WIDTH_G,
WRITE_MODE_A => ite(READ_LATENCY_G = 0, "read_first", "no_change"), -- Default value = no_change
WRITE_MODE_B => ite(READ_LATENCY_G = 0, "read_first", "no_change")) -- Default value = no_change
port map (
-- Port A
clka => clka,
ena => ena,
wea => wea,
regcea => regcea,
rsta => resetA,
addra => addra,
dina => dina,
douta => douta,
-- Port B
clkb => clkb,
enb => enb,
web => web,
regceb => regceb,
rstb => resetB,
addrb => addrb,
dinb => dinb,
doutb => doutb,
-- Misc.Interface
dbiterra => open,
dbiterrb => open,
sbiterra => open,
sbiterrb => open,
injectdbiterra => '0',
injectdbiterrb => '0',
injectsbiterra => '0',
injectsbiterrb => '0',
sleep => '0');

resetA <= rsta when(RST_POLARITY_G = '1') else not(rsta);
resetB <= rstb when(RST_POLARITY_G = '1') else not(rstb);

end rtl;
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