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Merge pull request #757 from slaclab/pre-release
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Release Candidate v2.11.0
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@ruck314
ruck314 authored Oct 26, 2020
2 parents 081638c + 738c464 commit ce09733
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Showing 29 changed files with 3,261 additions and 420 deletions.
117 changes: 67 additions & 50 deletions base/general/rtl/AsyncGearbox.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -19,44 +19,39 @@ use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;


library surf;
use surf.StdRtlPkg.all;

entity AsyncGearbox is

generic (
TPD_G : time := 1 ns;
SLAVE_WIDTH_G : positive;
SLAVE_BIT_REVERSE_G : boolean := false;
SLAVE_BIT_REVERSE_G : boolean := false;
MASTER_WIDTH_G : positive;
MASTER_BIT_REVERSE_G : boolean := false;
MASTER_BIT_REVERSE_G : boolean := false;
-- Pipelining generics
INPUT_PIPE_STAGES_G : natural := 0;
OUTPUT_PIPE_STAGES_G : natural := 0;
-- Async FIFO generics
FIFO_MEMORY_TYPE_G : string := "distributed";
FIFO_ADDR_WIDTH_G : positive := 4);
port (
slaveClk : in sl;
slaveRst : in sl;

-- input side data and flow control
slaveData : in slv(SLAVE_WIDTH_G-1 downto 0);
slaveValid : in sl := '1';
slaveReady : out sl;

-- sequencing and slip
slip : in sl := '0';

masterClk : in sl;
masterRst : in sl;

-- output side data and flow control
masterData : out slv(MASTER_WIDTH_G-1 downto 0);
masterValid : out sl;
masterReady : in sl := '1');

-- input side data and flow control (slaveClk domain)
slaveClk : in sl;
slaveRst : in sl;
slaveData : in slv(SLAVE_WIDTH_G-1 downto 0);
slaveValid : in sl := '1';
slaveReady : out sl;
slaveBitOrder : in sl := ite(SLAVE_BIT_REVERSE_G, '1', '0');
-- sequencing and slip (ASYNC input)
slip : in sl := '0';
-- output side data and flow control (masterClk domain)
masterClk : in sl;
masterRst : in sl;
masterData : out slv(MASTER_WIDTH_G-1 downto 0);
masterValid : out sl;
masterReady : in sl := '1';
masterBitOrder : in sl := ite(MASTER_BIT_REVERSE_G, '1', '0'));
end entity AsyncGearbox;

architecture mapping of AsyncGearbox is
Expand All @@ -66,15 +61,17 @@ architecture mapping of AsyncGearbox is
signal fastClk : sl;
signal fastRst : sl;

signal gearboxDataIn : slv(SLAVE_WIDTH_G-1 downto 0);
signal gearboxValidIn : sl;
signal gearboxReadyIn : sl;
signal gearboxDataOut : slv(MASTER_WIDTH_G-1 downto 0);
signal gearboxValidOut : sl;
signal gearboxReadyOut : sl;
signal gearboxSlip : sl;
signal almostFull : sl;
signal writeEnable : sl;
signal gearboxDataIn : slv(SLAVE_WIDTH_G-1 downto 0);
signal gearboxValidIn : sl;
signal gearboxReadyIn : sl;
signal gearboxDataOut : slv(MASTER_WIDTH_G-1 downto 0);
signal gearboxValidOut : sl;
signal gearboxReadyOut : sl;
signal gearboxSlip : sl;
signal gearboxSlaveBitOrder : sl;
signal gearboxMasterBitOrder : sl;
signal almostFull : sl;
signal writeEnable : sl;

begin

Expand All @@ -90,6 +87,24 @@ begin
dataIn => slip, -- [in]
dataOut => gearboxSlip); -- [out]

U_slaveBitOrder : entity surf.Synchronizer
generic map (
TPD_G => TPD_G,
INIT_G => ite(SLAVE_BIT_REVERSE_G, "11", "00"))
port map (
clk => fastClk,
dataIn => slaveBitOrder,
dataOut => gearboxSlaveBitOrder);

U_masterBitOrder : entity surf.Synchronizer
generic map (
TPD_G => TPD_G,
INIT_G => ite(MASTER_BIT_REVERSE_G, "11", "00"))
port map (
clk => fastClk,
dataIn => masterBitOrder,
dataOut => gearboxMasterBitOrder);

SLAVE_FIFO_GEN : if (not SLAVE_FASTER_C) generate
U_FifoAsync_1 : entity surf.FifoAsync
generic map (
Expand Down Expand Up @@ -142,15 +157,17 @@ begin
MASTER_WIDTH_G => MASTER_WIDTH_G,
MASTER_BIT_REVERSE_G => MASTER_BIT_REVERSE_G)
port map (
clk => fastClk, -- [in]
rst => fastRst, -- [in]
slaveData => gearboxDataIn, -- [in]
slaveValid => gearboxValidIn, -- [in]
slaveReady => gearboxReadyIn, -- [out]
masterData => gearboxDataOut, -- [out]
masterValid => gearboxValidOut, -- [out]
masterReady => gearboxReadyOut, -- [in]
slip => gearboxSlip); -- [in]
clk => fastClk, -- [in]
rst => fastRst, -- [in]
slaveData => gearboxDataIn, -- [in]
slaveValid => gearboxValidIn, -- [in]
slaveReady => gearboxReadyIn, -- [out]
slaveBitOrder => gearboxSlaveBitOrder, -- [in]
masterData => gearboxDataOut, -- [out]
masterValid => gearboxValidOut, -- [out]
masterReady => gearboxReadyOut, -- [in]
masterBitOrder => gearboxMasterBitOrder, -- [in]
slip => gearboxSlip); -- [in]

MASTER_FIFO_GEN : if (SLAVE_FASTER_C) generate
U_FifoAsync_1 : entity surf.FifoAsync
Expand All @@ -162,15 +179,15 @@ begin
PIPE_STAGES_G => OUTPUT_PIPE_STAGES_G,
ADDR_WIDTH_G => FIFO_ADDR_WIDTH_G)
port map (
rst => fastRst, -- [in]
wr_clk => fastClk, -- [in]
wr_en => writeEnable, -- [in]
din => gearboxDataOut, -- [in]
almost_full => almostFull, -- [out]
rd_clk => masterClk, -- [in]
rd_en => masterReady, -- [in]
dout => masterData, -- [out]
valid => masterValid); -- [out]
rst => fastRst, -- [in]
wr_clk => fastClk, -- [in]
wr_en => writeEnable, -- [in]
din => gearboxDataOut, -- [in]
almost_full => almostFull, -- [out]
rd_clk => masterClk, -- [in]
rd_en => masterReady, -- [in]
dout => masterData, -- [out]
valid => masterValid); -- [out]
gearboxReadyOut <= not(almostFull);
writeEnable <= gearboxValidOut and not(almostFull);
end generate MASTER_FIFO_GEN;
Expand Down
50 changes: 23 additions & 27 deletions base/general/rtl/Gearbox.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -19,37 +19,33 @@ use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;


library surf;
use surf.StdRtlPkg.all;

entity Gearbox is

generic (
TPD_G : time := 1 ns;
TPD_G : time := 1 ns;
SLAVE_BIT_REVERSE_G : boolean := false;
SLAVE_WIDTH_G : positive;
MASTER_BIT_REVERSE_G : boolean := false;
MASTER_WIDTH_G : positive);

port (
clk : in sl;
rst : in sl;

-- Clock and Reset
clk : in sl;
rst : in sl;
-- input side data and flow control
slaveData : in slv(SLAVE_WIDTH_G-1 downto 0);
slaveValid : in sl := '1';
slaveReady : out sl;

slaveData : in slv(SLAVE_WIDTH_G-1 downto 0);
slaveValid : in sl := '1';
slaveReady : out sl;
slaveBitOrder : in sl := ite(SLAVE_BIT_REVERSE_G, '1', '0');
-- sequencing and slip
startOfSeq : in sl := '0';
slip : in sl := '0';

startOfSeq : in sl := '0';
slip : in sl := '0';
-- output side data and flow control
masterData : out slv(MASTER_WIDTH_G-1 downto 0);
masterValid : out sl;
masterReady : in sl := '1');

masterData : out slv(MASTER_WIDTH_G-1 downto 0);
masterValid : out sl;
masterReady : in sl := '1';
masterBitOrder : in sl := ite(MASTER_BIT_REVERSE_G, '1', '0'));
end entity Gearbox;

architecture rtl of Gearbox is
Expand Down Expand Up @@ -80,7 +76,8 @@ architecture rtl of Gearbox is

begin

comb : process (slaveData, r, masterReady, rst, slip, startOfSeq, slaveValid) is
comb : process (masterBitOrder, masterReady, r, rst, slaveBitOrder,
slaveData, slaveValid, slip, startOfSeq) is
variable v : RegType;
begin
v := r;
Expand All @@ -98,12 +95,11 @@ begin
v.writeIndex := r.writeIndex - 1;
end if;


-- Only do anything if ready for data output
if (v.masterValid = '0') then

-- If current write index (assigned last cycle) is greater than output width,
-- then we have to shift down before assinging an new input
-- then we have to shift down before assigning an new input
if (v.writeIndex >= MASTER_WIDTH_G) then
v.shiftReg := slvZero(MASTER_WIDTH_G) & r.shiftReg(SHIFT_WIDTH_C-1 downto MASTER_WIDTH_G);
v.writeIndex := v.writeIndex - MASTER_WIDTH_G;
Expand All @@ -128,8 +124,8 @@ begin
-- Accept the input word
v.slaveReady := '1';

-- Assign incomming data at proper location in shift reg
if SLAVE_BIT_REVERSE_G then
-- Assign incoming data at proper location in shift reg
if (slaveBitOrder = '1') then
v.shiftReg(v.writeIndex+SLAVE_WIDTH_G-1 downto v.writeIndex) := bitReverse(slaveData);
else
v.shiftReg(v.writeIndex+SLAVE_WIDTH_G-1 downto v.writeIndex) := slaveData;
Expand All @@ -154,10 +150,10 @@ begin
rin <= v;

masterValid <= r.masterValid;
if MASTER_BIT_REVERSE_G then
masterData <= bitReverse(r.shiftReg(MASTER_WIDTH_G-1 downto 0));
if (masterBitOrder = '1') then
masterData <= bitReverse(r.shiftReg(MASTER_WIDTH_G-1 downto 0));
else
masterData <= r.shiftReg(MASTER_WIDTH_G-1 downto 0);
masterData <= r.shiftReg(MASTER_WIDTH_G-1 downto 0);
end if;

end process comb;
Expand All @@ -169,4 +165,4 @@ begin
end if;
end process sync;

end rtl;
end rtl;
17 changes: 3 additions & 14 deletions base/ram/inferred/DualPortRam.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -97,7 +97,7 @@ begin
end generate;

GEN_LUTRAM : if (MEMORY_TYPE_G="distributed") generate
QuadPortRam_Inst : entity surf.QuadPortRam
LutRam_Inst : entity surf.LutRam
generic map (
TPD_G => TPD_G,
RST_POLARITY_G => RST_POLARITY_G,
Expand All @@ -107,6 +107,7 @@ begin
DATA_WIDTH_G => DATA_WIDTH_G,
BYTE_WIDTH_G => BYTE_WIDTH_G,
ADDR_WIDTH_G => ADDR_WIDTH_G,
NUM_PORTS_G => 2,
INIT_G => INIT_G)
port map (
-- Port A
Expand All @@ -123,19 +124,7 @@ begin
en_b => enb,
rstb => rstb,
addrb => addrb,
doutb => doutb,
-- Port C
clkc => '0',
en_c => '0',
rstc => FORCE_RST_C,
addrc => (others => '0'),
doutc => open,
-- Port C
clkd => '0',
en_d => '0',
rstd => FORCE_RST_C,
addrd => (others => '0'),
doutd => open);
doutb => doutb);
end generate;

end mapping;
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