Merge pull request #313 from slaclab/pre-release

v1.9.0 release candidate
slaclab · Nov 6, 2018 · d616323 · d616323
2 parents f04df28 + 1fddc74
commit d616323
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diff --git a/axi/axi-lite/rtl/AxiDualPortRam.vhd b/axi/axi-lite/rtl/AxiDualPortRam.vhd
@@ -1,8 +1,6 @@
 -------------------------------------------------------------------------------
 -- File       : AxiDualPortRam.vhd
 -- Company    : SLAC National Accelerator Laboratory
--- Created    : 2013-12-17
--- Last update: 2018-03-09
 -------------------------------------------------------------------------------
 -- Description: A wrapper of StdLib DualPortRam that places an AxiLite
 -- interface on the read/write port. 
@@ -252,7 +250,11 @@ begin
       v.axiReadSlave.rdata := (others => '0');
 
       -- Multiplex read data onto axi bus
-      decAddrInt           := conv_integer(axiReadMaster.araddr(AXI_DEC_ADDR_RANGE_C));
+      if (DATA_WIDTH_G <= 32) then
+         decAddrInt := 0;
+      else
+         decAddrInt := conv_integer(axiReadMaster.araddr(AXI_DEC_ADDR_RANGE_C));
+      end if;
       v.axiReadSlave.rdata := axiDout((decAddrInt+1)*32-1 downto decAddrInt*32);
 
       -- Set axiAddr to read address by default
@@ -266,7 +268,11 @@ begin
             if (axiStatus.writeEnable = '1') then
                if (AXI_WR_EN_G) then
                   v.axiAddr  := axiWriteMaster.awaddr(AXI_RAM_ADDR_RANGE_C);
-                  decAddrInt := conv_integer(axiWriteMaster.awaddr(AXI_DEC_ADDR_RANGE_C));
+                  if (DATA_WIDTH_G <= 32) then
+                     decAddrInt := conv_integer(axiWriteMaster.awaddr(AXI_RAM_ADDR_RANGE_C));
+                  else
+                     decAddrInt := conv_integer(axiWriteMaster.awaddr(AXI_DEC_ADDR_RANGE_C));
+                  end if;
                   v.axiWrStrobe((decAddrInt+1)*4-1 downto decAddrInt*4) :=
                      axiWriteMaster.wstrb;
                end if;

diff --git a/axi/axi-lite/rtl/AxiLiteAsync.vhd b/axi/axi-lite/rtl/AxiLiteAsync.vhd
@@ -1,8 +1,6 @@
 -------------------------------------------------------------------------------
 -- File       : AxiLiteAsync.vhd
 -- Company    : SLAC National Accelerator Laboratory
--- Created    : 2013-04-02
--- Last update: 2017-11-07
 -------------------------------------------------------------------------------
 -- Description:
 -- Asynchronous bridge for AXI Lite bus. Allows AXI transactions to cross 

diff --git a/axi/axi-lite/rtl/AxiLiteCrossbar.vhd b/axi/axi-lite/rtl/AxiLiteCrossbar.vhd
@@ -1,8 +1,6 @@
 -------------------------------------------------------------------------------
 -- File       : AxiLiteCrossbar.vhd
 -- Company    : SLAC National Accelerator Laboratory
--- Created    : 2013-09-24
--- Last update: 2017-11-13
 -------------------------------------------------------------------------------
 -- Description: Wrapper around Xilinx generated Main AXI Crossbar for HPS Front End
 -------------------------------------------------------------------------------

diff --git a/axi/axi-lite/rtl/AxiLiteFifoPop.vhd b/axi/axi-lite/rtl/AxiLiteFifoPop.vhd
@@ -1,8 +1,6 @@
 -------------------------------------------------------------------------------
 -- File       : AxiLiteFifoPop.vhd
 -- Company    : SLAC National Accelerator Laboratory
--- Created    : 2013-04-02
--- Last update: 2016-04-26
 -------------------------------------------------------------------------------
 -- Description:
 -- Supports reading of general purpose FIFOs from the AxiLite bus.

diff --git a/axi/axi-lite/rtl/AxiLiteFifoPush.vhd b/axi/axi-lite/rtl/AxiLiteFifoPush.vhd
@@ -1,8 +1,6 @@
 -------------------------------------------------------------------------------
 -- File       : AxiLiteFifoPush.vhd
 -- Company    : SLAC National Accelerator Laboratory
--- Created    : 2013-04-02
--- Last update: 2016-04-26
 -------------------------------------------------------------------------------
 -- Description:
 -- Supports writing of general purpose FIFOs from the AxiLite bus.

diff --git a/axi/axi-lite/rtl/AxiLiteFifoPushPop.vhd b/axi/axi-lite/rtl/AxiLiteFifoPushPop.vhd
@@ -1,8 +1,6 @@
 -------------------------------------------------------------------------------
 -- File       : AxiLiteFifoPush.vhd
 -- Company    : SLAC National Accelerator Laboratory
--- Created    : 2013-04-02
--- Last update: 2016-04-26
 -------------------------------------------------------------------------------
 -- Description:
 -- Supports reading of general purpose FIFOs from the AxiLite bus.

diff --git a/axi/axi-lite/rtl/AxiLiteMaster.vhd b/axi/axi-lite/rtl/AxiLiteMaster.vhd
@@ -1,8 +1,6 @@
 -------------------------------------------------------------------------------
 -- File       : AxiLiteMaster.vhd
 -- Company    : SLAC National Accelerator Laboratory
--- Created    : 2014-04-09
--- Last update: 2016-03-09
 -------------------------------------------------------------------------------
 -- Description: AXI-Lite Master module controlled via REQ/ACK interface
 -------------------------------------------------------------------------------
@@ -22,17 +20,16 @@ use ieee.std_logic_unsigned.all;
 
 use work.StdRtlPkg.all;
 use work.AxiLitePkg.all;
-use work.AxiLiteMasterPkg.all;
 
 entity AxiLiteMaster is
    generic (
       -- General Config
       TPD_G : time := 1 ns);
    port (
-      axilClk          : in  sl;
-      axilRst          : in  sl;
-      req              : in  AxiLiteMasterReqType;
-      ack              : out AxiLiteMasterAckType;
+      axilClk         : in  sl;
+      axilRst         : in  sl;
+      req             : in  AxiLiteReqType;
+      ack             : out AxiLiteAckType;
       axilWriteMaster : out AxiLiteWriteMasterType;
       axilWriteSlave  : in  AxiLiteWriteSlaveType;
       axilReadMaster  : out AxiLiteReadMasterType;
@@ -46,14 +43,14 @@ architecture rtl of AxiLiteMaster is
    type StateType is (S_IDLE_C, S_WRITE_C, S_WRITE_AXI_C, S_READ_C, S_READ_AXI_C);
 
    type RegType is record
-      ack              : AxiLiteMasterAckType;
+      ack              : AxiLiteAckType;
       state            : StateType;
       axilWriteMaster : AxiLiteWriteMasterType;
       axilReadMaster  : AxiLiteReadMasterType;
    end record RegType;
 
    constant REG_INIT_C : RegType := (
-      ack              =>  AXI_LITE_MASTER_ACK_INIT_C,
+      ack              =>  AXI_LITE_ACK_INIT_C,
       state            => S_IDLE_C,
       axilWriteMaster => AXI_LITE_WRITE_MASTER_INIT_C,
       axilReadMaster  => AXI_LITE_READ_MASTER_INIT_C);
@@ -82,7 +79,7 @@ begin
             v.axilReadMaster  := AXI_LITE_READ_MASTER_INIT_C;
 
             if (req.request = '0') then
-               v.ack := AXI_LITE_MASTER_ACK_INIT_C;
+               v.ack := AXI_LITE_ACK_INIT_C;
             end if;
 
             -- Frame is starting

diff --git a/axi/axi-lite/rtl/AxiLiteMasterPkg.vhd b/axi/axi-lite/rtl/AxiLiteMasterPkg.vhd