Pull Requests

#313 - v1.9.0 release candidate
#301 - Adding PGPv3 support for GTP7
#293 - Remove Created and Last update comment header lines
#308 - Si5345 Support
#289 - Adding Ultrascale support for Ad9249
#304 - Updated AXI Stream from 128-bit to 512-bit
#303 - removing obsolete source code
#306 - Misc. Updates for EPIX Development
#281 - exposing ETH pause generic configurations
#331 - IP Bus to AXI-Lite bridge and AXI-Lite to IP Bus bridge
#334 - Updates to SURF from ATLAS ALTIROC development
#283 - removing duplicated code that's used in both UltraScale and UltraScale+
#312 - Apply fixes to yaml files needed for CPSW tools
#296 - ADC32RF45 and RssiWrapper Updates
#329 - Support for 128bit descriptors in DMA engine.
#327 - Adding AxiRam and its simulation testbed
#300 - Asynchronous Gearbox
#282 - Update for LMK/DAC init sequence for cryo, use pulsed SysRef
#294 - AxiStream Batcher Version1
#309 - Remove AxiStreamPacketizerMux
#292 - Rogue device tweaks
#291 - Add a generic Gearbox module
#330 - Adding inferred RAM support to AxiRam.vhd
#280 - I2C Cleanup
#316 - Add AxiStreamRepeater.vhd
#288 - Re-coding axiSlaveRegister to not use recursion
#279 - Propagate RSSI Segment Size to the Packetizer
#298 - Depreciating surf.misc.GenericMemory.py
#332 - Depreciating AxiStreamBatcherEventBuilder's Event Interface
#311 - adding SyncTrigPeriod.vhd
#299 - deprecating the optional mAxisMaster interface
#273 - bug fix to TX gmii preamble
#322 - RSSI: Connecting RX buffer full to RssiMonitor.vhd
#290 - updating linkrate and linkwidth to LinkVariables
#310 - migrating from GenericMemory to MemoryDevice
#268 - removing location constraints in the .DCP files
#270 - corner case bug fix for AxiMicronN25Q.py
#328 - Add arprot/awprot support to SRPv3
#315 - SyncTrigPeriod.vhd Bug fix
#271 - Catch read error in AxiVersion
#284 - Make axiSlaveRegisterR() ignore write requests instead of responding with OK
#305 - Add option to run XADC DRP at a different clock than axilClk
#333 - Resolved Vivado syntax warnings and critical warning messages for SURF's I2C lib
#262 - depreciating unused AXI stream interface
#325 - fix the python file names to CamalCase
#276 - Fix VCS warning due to use other (others => ...)
#277 - Add notes for setting gtx7 clocks
#324 - Resolved null assignment in AxiDualPortRam.vhd
#314 - Python devices.ti Update
#287 - fixed false output transition after reset
#326 - Fixed broken SRPv3AxiLiteFull.vhd module
#272 - Update PyRogue
#318 - Bad descriptor return size for read buffers
#274 - Fix mismatched function declaration
#295 - Lmk04828.py Update
#286 - fixing genAxiLiteConfig declaration
#317 - Bad size constant for AxiWriteDmaDescAckType
#307 - Fix comma in python
#302 - Fix 8-byte fixed size in endianSwap()
#285 - Dac38J84.py bug fix
#319 - Cut and paste error

Pull Request Details

v1.9.0 release candidate


Author:	Larry Ruckman [email protected]
Date:	Tue Nov 6 11:10:26 2018 -0800
Pull:	#313 (18650 additions, 7932 deletions, 708 files changed)
Branch:	slaclab/pre-release

Notes:

Description

Major Change: Updated AXI Stream from 128-bit to 512-bit (#304)

bug fix to TX gmii preamble (#273)

removing location constraints in the .DCP files (#268)

depreciating unused AXI stream interface (#262)

corner case bug fix for AxiMicronN25Q.py (#270)

Fix mismatched function declaration (#274)

Fix VCS warning due to use other (others => ...) (#276)

Add notes for setting gtx7 clocks (#277)

Update for LMK/DAC init sequence for cryo, use pulsed SysRef (#282)

Dac38J84.py bug fix (#285)

fixing genAxiLiteConfig declaration (#286)

fixed false output transition after reset (#287)

I2C Cleanup (#280)

removing duplicated code that's used in both UltraScale and UltraScale+ (#283)

exposing ETH pause generic configurations (#281)

Adding Ultrascale support for Ad9249 (#289)

Re-coding axiSlaveRegister to not use recursion (#288)

updating linkrate and linkwidth to LinkVariables for AxiPciePhy.py (#290)

Remove Created and Last update comment header lines (#293)

Rogue device tweaks (#292)

Add a generic Gearbox module (#291)

Fix 8-byte fixed size in endianSwap (#302)

Adding Asynchronous Gearbox (#300)

deprecating the optional mAxisMaster interface for SsiPrbsRx.vhd (#299)

Added AxiStream Batcher Version1 (#294)

Fix comma in python (#307)

Add option to run XADC DRP at a different clock than axilClk (#305)

Remove AxiStreamPacketizerMux (#309)

removing obsolete source code (#303)

Depreciating surf.misc.GenericMemory.py (#298)

Misc. Updates for EPIX Development (#306)

Make axiSlaveRegisterR() ignore write requests instead of responding with OK (#284)

Si5345 Support (#308)

Lmk04828.py Update (#295)

Adding PGPv3 support for GTP7 (#301)

ADC32RF45 and RssiWrapper Updates (#296)

migrating from GenericMemory to MemoryDevice (#310)

Apply fixes to yaml files needed for CPSW tools (#312)

Catch read error in AxiVersion (#272)

adding SyncTrigPeriod.vhd (#311)

Propagate RSSI Segment Size to the Packetizer (#279)

Connecting RX buffer full to RssiMonitor.vhd (#322)

Adding AxiRam and its simulation testbed (#327)

Add arprot/awprot support to SRPv3 (#328)

fix the python file names to CamalCase (#325)

Resolved null assignment in AxiDualPortRam.vhd (#324)

IP Bus to AXI-Lite bridge and AXI-Lite to IP Bus bridgeAxiDualPortRam.vhd (#331)

Support for 128bit descriptors in DMA engine (#329)

Resolved Vivado syntax warnings and critical warning messages for SURF's I2C lib (#333)

Adding inferred RAM support to AxiRam.vhd (#330)

Fixed broken SRPv3AxiLiteFull.vhd module (#326)

Updates to SURF from ATLAS ALTIROC development (#334)

Adding PGPv3 support for GTP7


Author:	Larry Ruckman [email protected]
Date:	Thu Oct 11 16:30:58 2018 -0700
Pull:	#301 (4923 additions, 63 deletions, 27 files changed)
Branch:	slaclab/PGPv3-gtp7

Notes:

Description

Adding PGPv3 support for GTP7

Fixed a rounding error in MmcmEmulation.vhd

Fixed a bug in MmcmEmulation.vhd that would lock up during the phasing up process if clock stops and RST=0x1

Remove Created and Last update comment header lines


Author:	Benjamin Reese [email protected]
Date:	Tue Sep 18 11:24:12 2018 -0700
Pull:	#293 (1069 additions, 2193 deletions, 575 files changed)
Branch:	slaclab/rem-update-date

Notes:

The lines with
-- Created    : xxx
-- Last update: xxx
Were tending to cause merge conflicts.

Git tracks this info anyway, so I wrote a script to remove them from every *.vhd file.

The script also changed everything to Unix style line endings if it wasn't already.

Si5345 Support


Author:	Benjamin Reese [email protected]
Date:	Thu Oct 11 16:18:55 2018 -0700
Pull:	#308 (2999 additions, 0 deletions, 6 files changed)
Branch:	slaclab/Si5345-dev

Notes:

Description

Adding Si5345 Support support

Added InputBufferReg/OutputBufferReg for 7 series

Adding Ultrascale support for Ad9249


Author:	Benjamin Reese [email protected]
Date:	Tue Sep 11 16:06:32 2018 -0700
Pull:	#289 (1843 additions, 69 deletions, 17 files changed)
Branch:	slaclab/ad9249Ultrascale

Notes:

Description

Adding Ultrascale support for Ad9249

Updated AXI Stream from 128-bit to 512-bit


Author:	Larry Ruckman [email protected]
Date:	Fri Oct 26 11:13:29 2018 -0700
Pull:	#304 (1142 additions, 422 deletions, 49 files changed)
Branch:	slaclab/axi-stream-wider

Notes:

Description

Fixing all the SURF source code that has assumption of 128-bit AXIS

In AxiStreamPkg.vhd, created AXI_STREAM_MAX_TDATA_WIDTH_C=512. If we have to upgrade again, we can increase this single constant which will cascade to all the other source code.

Adding AxiResize.vhd

removing obsolete source code


Author:	Larry Ruckman [email protected]
Date:	Tue Oct 9 11:27:04 2018 -0700
Pull:	#303 (0 additions, 1520 deletions, 4 files changed)
Branch:	slaclab/jesd-example

Notes:

Description

removing obsolete source code

Misc. Updates for EPIX Development


Author:	Larry Ruckman [email protected]
Date:	Thu Oct 11 16:02:40 2018 -0700
Pull:	#306 (837 additions, 287 deletions, 15 files changed)
Branch:	slaclab/epix-dev

Notes:

Description

Additional diagnostic registers for AxiMemTester.vhd

Added python/surf/devices/cypress/CypressS25Fl

Updates to devices/AnalogDevices/ad9249

exposing ETH pause generic configurations


Author:	Larry Ruckman [email protected]
Date:	Fri Sep 7 16:18:08 2018 -0700
Pull:	#281 (587 additions, 451 deletions, 34 files changed)
Branch:	slaclab/eth-pause

Notes:

Description

exposing ETH pause generic configurations for 10GBase-KX4

exposing ETH pause generic configurations for 10GBase-KR

exposing ETH pause generic configurations for 1000BASE-KX

Note:

Exposing the ETH pause to let us experiment with pauses enabled/disabled with the Advantech switch

IP Bus to AXI-Lite bridge and AXI-Lite to IP Bus bridge


Author:	Larry Ruckman [email protected]
Date:	Tue Oct 30 10:28:30 2018 -0700
Pull:	#331 (725 additions, 79 deletions, 14 files changed)
Branch:	slaclab/ESCORE-58
Jira:	https://jira.slac.stanford.edu/issues/ESCORE-58

Notes:

Description

Depreciated AxiLiteMasterPkg.vhd (migrated types and constants to AxiLiteMasterPkg.vhd)

Added axi-lite/AxiLiteSlave.vhd (uses the same types and cosntants in legacy AxiLiteMasterPkg.vhd)

Added the AxiLiteToIpBus.vhd & IpBusToAxiLite.vhd modules

Added AxiLiteIpBusBridgeTb.vhd simulation testbed

JIRA

ESCORE-58

Updates to SURF from ATLAS ALTIROC development


Author:	Larry Ruckman [email protected]
Date:	Tue Nov 6 10:17:32 2018 -0800
Pull:	#334 (479 additions, 241 deletions, 6 files changed)
Branch:	slaclab/atlas-altiroc-dev

Notes:

Description

Polishing the python/VHDL for Si5345

Adding free running clock support to SpiMaster.vhd

In AxiVersion, polishing UpTime LinkVar and setting FdSerial to hidden

Hiding Ltc4151.Control RemoteVar

Adding Sa56004x.simpleView support

removing duplicated code that's used in both UltraScale and UltraScale+


Author:	Larry Ruckman [email protected]
Date:	Fri Sep 7 16:17:57 2018 -0700
Pull:	#283 (1 additions, 697 deletions, 5 files changed)
Branch:	slaclab/UltraScale-update

Notes:

Description

removing duplicated code that's used in both UltraScale and UltraScale+

Apply fixes to yaml files needed for CPSW tools


Author:	Larry Ruckman [email protected]
Date:	Tue Oct 16 09:24:45 2018 -0700
Pull:	#312 (335 additions, 319 deletions, 11 files changed)
Branch:	slaclab/lcls2prl-yaml-fixes

Notes:

Description

Apply fixes to yaml files needed for CPSW tools

ADC32RF45 and RssiWrapper Updates


Author:	Larry Ruckman [email protected]
Date:	Thu Oct 11 16:48:18 2018 -0700
Pull:	#296 (459 additions, 186 deletions, 3 files changed)
Branch:	slaclab/Adc32Rf45-dev

Notes:

Description

Updates to the adc32rf45.vhd (advance mode access)

Updates to the _adc32Rf45.py for this new access mode

Bring ILEAVE_ON_NOTVALID_G in RssiWrapper.vhd to top-level (default=false for same behavior)

Support for 128bit descriptors in DMA engine.


Author:	Larry Ruckman [email protected]
Date:	Thu Nov 1 13:03:57 2018 -0700
Pull:	#329 (325 additions, 221 deletions, 23 files changed)
Branch:	slaclab/128bit-desc

Notes:

This PR updates the axis version2 dma engine to support 128 bit descriptors. The engine is compatible with the existing drivers when running in 64-bit mode. The latest version of the driver is required for 128bit mode operation.

Adding AxiRam and its simulation testbed


Author:	Larry Ruckman [email protected]
Date:	Fri Oct 26 11:10:57 2018 -0700
Pull:	#327 (525 additions, 0 deletions, 2 files changed)
Branch:	slaclab/ESCORE-260
Jira:	https://jira.slac.stanford.edu/issues/ESCORE-260

Notes:

Description

Adding AxiRam and its simulation testbed

JIRA

ESCORE-260

Asynchronous Gearbox


Author:	Larry Ruckman [email protected]
Date:	Fri Sep 28 14:16:11 2018 -0700
Pull:	#300 (341 additions, 115 deletions, 3 files changed)
Branch:	slaclab/gearbox

Notes:

Description

Created AsyncGearbox to transition between clock domains along with data widths.

Also renamed Gearbox ports to use master/slave naming.

Details

The AsyncGearbox has in internal Gearbox that runs on whichever clock is faster. The side with the smaller data width will have the faster clock. An asynchronous FIFO is placed before the gearbox if the master (output) side is faster, or after the gearbox if the slave (input) side is faster.

It is recommended that the two clocks be perfect ratios of each other relative to the data widths. For applications such as GTs that require input or output acceptance every cycle, both clocks should be created from the same PLL/MMCM.

Example clock speeds:

SLAVE_WIDTH_G = 10
MASTER_WIDTH_G = 8
Master (output) side is faster.
slaveClk = 10 ns = 100 MHz
masterClk = 8 ns = 125 MHz

Update for LMK/DAC init sequence for cryo, use pulsed SysRef


Author:	Larry Ruckman [email protected]
Date:	Wed Aug 29 12:37:18 2018 -0700
Pull:	#282 (261 additions, 176 deletions, 2 files changed)
Branch:	slaclab/mdewart-cryo

Notes:

Update LMK and DAC38J84 PyRogue initialization

Description

Update LMK initialization procedure to match DAC38J84 EVM GUI
Use pulsed sysref

Details

JIRA

Related

AxiStream Batcher Version1


Author:	Larry Ruckman [email protected]
Date:	Fri Oct 5 11:14:10 2018 -0700
Pull:	#294 (423 additions, 0 deletions, 3 files changed)
Branch:	slaclab/AxiStreamBatcher

Notes:

Description

Adding protocols/AxiStreamBatcher.vhd

Notes

Protocol Defination

JIRA

ESCORE-383

Remove AxiStreamPacketizerMux


Author:	Larry Ruckman [email protected]
Date:	Tue Oct 9 11:23:52 2018 -0700
Pull:	#309 (0 additions, 342 deletions, 1 files changed)
Branch:	slaclab/ben-cleanup

Notes:

Description

This module was a first pass at what is now AxiStreamPacketizer2. It was never tested and doesn't even work. It hung around because I forgot about it.

Rogue device tweaks


Author:	Benjamin Reese [email protected]
Date:	Tue Sep 18 11:24:50 2018 -0700
Pull:	#292 (271 additions, 63 deletions, 5 files changed)
Branch:	slaclab/rogue-device-tweaks

Notes:

Description

Several Rogue devices have been added or tweaked in small ways.

Details

Mostly making registers 'RO' when they should be or adjusting disp= displays.
This is an accumulation of tweaks applied during development in other projects, namely HPS.

Add a generic Gearbox module


Author:	Benjamin Reese [email protected]
Date:	Wed Sep 19 15:13:28 2018 -0700
Pull:	#291 (322 additions, 0 deletions, 2 files changed)
Branch:	slaclab/gearbox

Notes:

Description

A generic gearbox that works with input and output words of any size.

Details

Uses valid/ready handshaking for flow control.

Slip feature allows bits to be dropped in order to perform word alignment.

No limit on input and output widths.

Want to go 5 bits to 67 bits, or 128 bits to 3 bits? Knock yourself out.

Simulation testbench has been run with several different size combinations and seems to work well.

Potential uses

32 <-> 66 for 64b66b on 32-bit wide GTP7 transceivers.

8 <-> 10 for 8b10b on Ultrascale SERDES primitives.

8 <-> x for anything on Ultrascale SERDES primitives.

Adding inferred RAM support to AxiRam.vhd


Author:	Larry Ruckman [email protected]
Date:	Mon Nov 5 13:31:49 2018 -0800
Pull:	#330 (254 additions, 55 deletions, 10 files changed)
Branch:	slaclab/AxiRam-inferred

Notes:

Description

adding inferred RAM support to AxiRam.vhd (default inferred)

I2C Cleanup


Author:	Benjamin Reese [email protected]
Date:	Fri Sep 7 16:17:16 2018 -0700
Pull:	#280 (20 additions, 253 deletions, 4 files changed)
Branch:	slaclab/i2c-rem-dup

Notes:

Description

Removed AxiI2cMasterCore.

This module was a functional duplicate of AxiI2cRegMaster.
Not sure how we never noticed but we should remove it now to avoid future confusion.

Removed USER register functionality from I2cRegMasterAxiBridge

No one was using it and it made the code rather confusing and messy.

Add AxiStreamRepeater.vhd


Author:	Benjamin Reese [email protected]
Date:	Mon Oct 22 09:57:07 2018 -0700
Pull:	#316 (180 additions, 0 deletions, 1 files changed)
Branch:	slaclab/AxiStreamRepeater

Notes:

Description

Add AxiStreamRepeater.vhd module to connect a single incoming AXI stream to multiple outgoing AXI streams

Re-coding axiSlaveRegister to not use recursion


Author:	Larry Ruckman [email protected]
Date:	Thu Sep 13 11:36:33 2018 -0700
Pull:	#288 (142 additions, 36 deletions, 4 files changed)
Branch:	slaclab/ESCORE-147
Jira:	https://jira.slac.stanford.edu/issues/ESCORE-147

Notes:

Description

Re-coding axiSlaveRegister to not use recursion

JIRA

ESCORE-147

Propagate RSSI Segment Size to the Packetizer


Author:	Larry Ruckman [email protected]
Date:	Mon Oct 22 09:50:46 2018 -0700
Pull:	#279 (112 additions, 29 deletions, 5 files changed)
Branch:	slaclab/ESLCOMMON-229
Jira:	https://jira.slac.stanford.edu/issues/ESLCOMMON-229

Notes:

Propagate RSSI Segment Size to the Packetizer

Description

During a RSSI connection negotiation the peer communicates the max. segment size it can accept to FW (and vice versa). This patch propagates this information to the packetizer so that fragments do not exceed the maximum that is acceptable to the peer.

Details

Small changes were made to RSSI (added output which provides the peer's max. segment size) and the packetizers (the fragment size can be set dynamically rather than by generic; if the new input is unused then it is optimized away and the module works as always).

Note that the changes in code and added resource requirements are minimal. All code is fully backwards-compatible.

JIRA

https://jira.slac.stanford.edu/browse/ESLCOMMON-229

Related

Might help resolve
https://jira.slac.stanford.edu/browse/ESLCOMMON-228 since it makes sure the system works even if software is not configured for jumbo frames. Software can set its advertised RSSI segment size based on the interface MTU. This patch then causes firmware to program the packetizer so that it doesn't exceed the segment size.

Depreciating surf.misc.GenericMemory.py


Author:	Larry Ruckman [email protected]
Date:	Thu Oct 11 15:53:04 2018 -0700
Pull:	#298 (0 additions, 137 deletions, 2 files changed)
Branch:	slaclab/ESROGUE-288
Jira:	https://jira.slac.stanford.edu/issues/ESROGUE-288

Notes:

Description

Depreciating surf.misc.GenericMemory.py

JIRA

ESROGUE-288

Depreciating AxiStreamBatcherEventBuilder's Event Interface


Author:	Larry Ruckman [email protected]
Date:	Wed Oct 31 13:04:09 2018 -0700
Pull:	#332 (35 additions, 100 deletions, 1 files changed)
Branch:	slaclab/AxiStreamBatcherEventBuilder-dev

Notes:

Description

Depreciating AxiStreamBatcherEventBuilder's Event Interface

Using NULL frames to drop AXIS stream frames at the AxiStreamBatcherEventBuilder instead

adding SyncTrigPeriod.vhd


Author:	Larry Ruckman [email protected]
Date:	Tue Oct 16 11:14:49 2018 -0700
Pull:	#311 (133 additions, 0 deletions, 1 files changed)
Branch:	slaclab/SyncTrigPeriod

Notes:

Description

adding module to monitor the period statistics between triggers

deprecating the optional mAxisMaster interface


Author:	Larry Ruckman [email protected]
Date:	Fri Oct 5 11:13:52 2018 -0700
Pull:	#299 (8 additions, 109 deletions, 1 files changed)
Branch:	slaclab/SsiPrbsRx-update

Notes:

Description

Deprecating the optional mAxisMaster interface

This mAxisMaster interface didn't optmize away when unused, sometimes unable to make timing for slower FPGA fabrics (like Artix-7) and not used by anyone

bug fix to TX gmii preamble


Author:	Larry Ruckman [email protected]
Date:	Tue Aug 14 16:00:40 2018 -0700
Pull:	#273 (40 additions, 49 deletions, 1 files changed)
Branch:	slaclab/gmii-preamble

Notes:

Description

bug fix to TX gmii preamble

RSSI: Connecting RX buffer full to RssiMonitor.vhd


Author:	Larry Ruckman [email protected]
Date:	Fri Oct 26 11:10:37 2018 -0700
Pull:	#322 (52 additions, 19 deletions, 4 files changed)
Branch:	slaclab/ESLCOMMON-236
Jira:	https://jira.slac.stanford.edu/issues/ESLCOMMON-236

Notes:

Description

Connecting RX buffer full to RssiMonitor.vhd

JIRA

ESLCOMMON-236

updating linkrate and linkwidth to LinkVariables


Author:	Larry Ruckman [email protected]
Date:	Mon Sep 17 16:38:55 2018 -0700
Pull:	#290 (47 additions, 18 deletions, 1 files changed)
Branch:	slaclab/AxiPciePhy

Notes:

Description

updating linkrate and linkwidth to LinkVariables

migrating from GenericMemory to MemoryDevice


Author:	Larry Ruckman [email protected]
Date:	Fri Oct 12 09:13:06 2018 -0700
Pull:	#310 (24 additions, 26 deletions, 2 files changed)
Branch:	slaclab/MemoryDevice-update

Notes:

Description

migrating from GenericMemory to MemoryDevice

removing location constraints in the .DCP files


Author:	Larry Ruckman [email protected]
Date:	Tue Aug 14 16:01:49 2018 -0700
Pull:	#268 (31 additions, 14 deletions, 4 files changed)
Branch:	slaclab/Gty-loc

Notes:

Description

removing location constraints in the .DCP files

corner case bug fix for AxiMicronN25Q.py


Author:	Larry Ruckman [email protected]
Date:	Tue Aug 14 16:15:05 2018 -0700
Pull:	#270 (21 additions, 21 deletions, 1 files changed)
Branch:	slaclab/ESCORE-370
Jira:	https://jira.slac.stanford.edu/issues/ESCORE-370

Notes:

Description

corner case bug fixes for AxiMicronN25Q.py

JIRA

ESCORE-370

Add arprot/awprot support to SRPv3


Author:	Larry Ruckman [email protected]
Date:	Fri Oct 26 11:11:59 2018 -0700
Pull:	#328 (29 additions, 12 deletions, 8 files changed)
Branch:	slaclab/ESCORE-398
Jira:	https://jira.slac.stanford.edu/issues/ESCORE-398

Notes:

Description

Add arprot/awprot support to SRPv3

JIRA

ESCORE-398

Related

The public domain documentation has been updated as well:
https://confluence.slac.stanford.edu/x/cRmVD

SyncTrigPeriod.vhd Bug fix


Author:	Benjamin Reese [email protected]
Date:	Mon Oct 22 09:57:24 2018 -0700
Pull:	#315 (24 additions, 12 deletions, 1 files changed)
Branch:	slaclab/SyncTrigPeriod

Notes:

Description

Bug fix for period measurements after reset

Catch read error in AxiVersion


Author:	Larry Ruckman [email protected]
Date:	Thu Aug 9 15:22:06 2018 -0700
Pull:	#271 (19 additions, 15 deletions, 1 files changed)
Branch:	slaclab/ESCORE-372
Jira:	https://jira.slac.stanford.edu/issues/ESCORE-372

Notes:

This PR fixes an error which occurs when a read timeout occurs at startup.

Make axiSlaveRegisterR() ignore write requests instead of responding with OK


Author:	Benjamin Reese [email protected]
Date:	Thu Oct 11 16:03:14 2018 -0700
Pull:	#284 (17 additions, 15 deletions, 1 files changed)
Branch:	slaclab/ESCORE-381
Jira:	https://jira.slac.stanford.edu/issues/ESCORE-381

Notes:

Description

The implementation of axiSlaveRegisterR was such that it would always respond with AXI_RESP_OK in response to requests on the write bus. Most of the time this doesn't hurt, but it isn't necessarily correct. A parameter has been added to allow the function to ignore write requests.

JIRA

https://jira.slac.stanford.edu/browse/ESCORE-381

Add option to run XADC DRP at a different clock than axilClk


Author:	Benjamin Reese [email protected]
Date:	Tue Oct 9 09:51:32 2018 -0700
Pull:	#305 (22 additions, 7 deletions, 1 files changed)
Branch:	slaclab/xadc-dev

Notes:

Description

A new COMMON_CLOCK_G generic and xadcClk, xadcRst inputs have been added to XadcSimpleCore.

Details

I ran in to a situation where the AXIL clock was 200 MHz, but the Kintex7 DRP can run that fast. This change simply exposes more functionality of the underlying AxiLiteDrp to allow the DRP interface to run on a different clock than the attached AXI-Lite clock.

Resolved Vivado syntax warnings and critical warning messages for SURF's I2C lib


Author:	Larry Ruckman [email protected]
Date:	Mon Nov 5 13:29:32 2018 -0800
Pull:	#333 (11 additions, 11 deletions, 2 files changed)
Branch:	slaclab/ESCORE-399
Jira:	https://jira.slac.stanford.edu/issues/ESCORE-399

Notes:

Description

Resolved Vivado syntax warnings and critical warning messages for SURF's I2C lib

JIRA

ESCORE-399

depreciating unused AXI stream interface


Author:	Larry Ruckman [email protected]
Date:	Tue Aug 14 16:05:48 2018 -0700
Pull:	#262 (1 additions, 21 deletions, 2 files changed)
Branch:	slaclab/ESCORE-364
Jira:	https://jira.slac.stanford.edu/issues/ESCORE-364

Notes:

Description

depreciating unused AXI stream interface

JIRA

ESCORE-364

fix the python file names to CamalCase


Author:	Larry Ruckman [email protected]
Date:	Thu Oct 25 11:35:18 2018 -0700
Pull:	#325 (10 additions, 10 deletions, 16 files changed)
Branch:	slaclab/ESCORE-379
Jira:	https://jira.slac.stanford.edu/issues/ESCORE-379

Notes:

Description

fix the python file names to CamalCase

JIRA

ESCORE-379

Fix VCS warning due to use other (others => ...)


Author:	Benjamin Reese [email protected]
Date:	Mon Aug 20 17:08:24 2018 -0700
Pull:	#276 (11 additions, 9 deletions, 1 files changed)
Branch:	slaclab/gig-eth-gtp-fix

Notes:

Description

VCS doesn't like use of (others => signalName) in port mappings. Technically you can only use (others => ...) with static values.

Related

There are probably several other instances of this in SURF. We should look for them.

Add notes for setting gtx7 clocks


Author:	Larry Ruckman [email protected]
Date:	Tue Aug 28 12:12:30 2018 -0700
Pull:	#277 (14 additions, 0 deletions, 1 files changed)
Branch:	slaclab/gtx_notes

Notes:

We should do this in other code as well that has complex settings that people will need to adjust.

Resolved null assignment in AxiDualPortRam.vhd


Author:	Larry Ruckman [email protected]
Date:	Thu Oct 25 11:35:03 2018 -0700
Pull:	#324 (10 additions, 2 deletions, 1 files changed)
Branch:	slaclab/ESCORE-317
Jira:	https://jira.slac.stanford.edu/issues/ESCORE-317

Notes:

Description

Resolved NULL assignment in AxiDualPortRam.vhd

JIRA

ESCORE-317

Python devices.ti Update


Author:	Benjamin Reese [email protected]
Date:	Mon Oct 22 09:57:37 2018 -0700
Pull:	#314 (6 additions, 6 deletions, 2 files changed)
Branch:	slaclab/python-device-ti

Notes:

Description

After grep-ing the python, these were the last pieces of python code that used this old method for doing "import"

fixed false output transition after reset


Author:	Benjamin Reese [email protected]
Date:	Thu Sep 6 12:11:08 2018 -0700
Pull:	#287 (6 additions, 5 deletions, 1 files changed)
Branch:	slaclab/epix-dev

Notes:

Description

Fixing the debouncer that is falsely flipping its output when the input is high during reset

Fixed broken SRPv3AxiLiteFull.vhd module


Author:	Larry Ruckman [email protected]
Date:	Mon Nov 5 14:05:26 2018 -0800
Pull:	#326 (5 additions, 5 deletions, 3 files changed)
Branch:	slaclab/ESCORE-186
Jira:	https://jira.slac.stanford.edu/issues/ESCORE-186

Notes:

Description

Fixed the bug where the FIFO address was out-of-range. In SRPv3AxiLiteFull, the FIFO address was 1. Now the AxiStreamDmaWrite will prevent FIFO address size < 4

JIRA

ESCORE-186

Update PyRogue


Author:	Larry Ruckman [email protected]
Date:	Fri Aug 10 11:58:10 2018 -0700
Pull:	#272 (4 additions, 4 deletions, 1 files changed)
Branch:	slaclab/jmdewart-patch-1

Notes:

Description

Details

JIRA

Related

Bad descriptor return size for read buffers


Author:	Larry Ruckman [email protected]
Date:	Fri Oct 19 08:46:48 2018 -0700
Pull:	#318 (5 additions, 1 deletions, 1 files changed)
Branch:	slaclab/ESCORE-393
Jira:	https://jira.slac.stanford.edu/issues/ESCORE-393

Notes:

Bad descriptor return size for read buffers in AxiStreamDmaV2Desc

Fix mismatched function declaration


Author:	Benjamin Reese [email protected]
Date:	Mon Aug 20 10:52:56 2018 -0700
Pull:	#274 (3 additions, 3 deletions, 1 files changed)
Branch:	slaclab/axi-lite-pkg-fix

Notes:

Description

This was introduced in commit 83b7079, #260.

Xilinx synthesis doesn't report it as an error, so no one noticed until I tried to simulate it.

Related

#260

Lmk04828.py Update


Author:	Benjamin Reese [email protected]
Date:	Thu Oct 11 16:23:34 2018 -0700
Pull:	#295 (4 additions, 1 deletions, 1 files changed)
Branch:	slaclab/Lmk04828-update

Notes:

Description

adding support for both pulse and continuous sysref mode

fixing genAxiLiteConfig declaration


Author:	Larry Ruckman [email protected]
Date:	Tue Sep 4 13:47:54 2018 -0700
Pull:	#286 (2 additions, 2 deletions, 1 files changed)
Branch:	slaclab/epix-dev

Notes:

Description

In the previous change to the AxiLitPkg.vhd parameters of the genAxiLiteConfig were modified in the package body, but not in the function declaration. The mismatch was causing the VCS to fail the compilation. The vivado build didn't mind the mismatch.

Bad size constant for AxiWriteDmaDescAckType


Author:	Larry Ruckman [email protected]
Date:	Fri Oct 19 08:47:08 2018 -0700
Pull:	#317 (1 additions, 1 deletions, 1 files changed)
Branch:	slaclab/ESCORE-392
Jira:	https://jira.slac.stanford.edu/issues/ESCORE-392

Notes:

Bad size constant for AxiWriteDmaDescAckType

Fix comma in python


Author:	Larry Ruckman [email protected]
Date:	Tue Oct 9 09:24:51 2018 -0700
Pull:	#307 (1 additions, 1 deletions, 1 files changed)
Branch:	slaclab/mdewart-cryo

Notes:

Description

Fix comma in python

Fix 8-byte fixed size in endianSwap()


Author:	Benjamin Reese [email protected]
Date:	Thu Sep 27 09:58:43 2018 -0700
Pull:	#302 (1 additions, 1 deletions, 1 files changed)
Branch:	slaclab/endian-swap

Notes:

Description

The endian swap function had a bug that effectively required the input size to be 64 bits (8 bytes). This has been fixed.

Thanks to @ulegat for finding this.

Dac38J84.py bug fix


Author:	Larry Ruckman [email protected]
Date:	Fri Aug 31 14:17:08 2018 -0700
Pull:	#285 (1 additions, 1 deletions, 1 files changed)
Branch:	slaclab/Dac38J84-bug-fix

Notes:

Description

Dac38J84.py bug fix

Cut and paste error


Author:	Larry Ruckman [email protected]
Date:	Fri Oct 19 08:46:28 2018 -0700
Pull:	#319 (0 additions, 1 deletions, 1 files changed)
Branch:	slaclab/ESCORE-394
Jira:	https://jira.slac.stanford.edu/issues/ESCORE-394

Notes:

Cut and paste error in AxiStreamDmaV2Desc which sets the write ack address at the wrong place.

Minor Release

Pull Requests

Pull Request Details

v1.9.0 release candidate

Description

Adding PGPv3 support for GTP7

Description

Remove Created and Last update comment header lines

Si5345 Support

Description

Adding Ultrascale support for Ad9249

Description

Updated AXI Stream from 128-bit to 512-bit

Description

removing obsolete source code

Description

Misc. Updates for EPIX Development

Description

exposing ETH pause generic configurations

Description

Note:

IP Bus to AXI-Lite bridge and AXI-Lite to IP Bus bridge

Description

JIRA

Updates to SURF from ATLAS ALTIROC development

Description

removing duplicated code that's used in both UltraScale and UltraScale+

Description

Apply fixes to yaml files needed for CPSW tools

Description

ADC32RF45 and RssiWrapper Updates

Description

Support for 128bit descriptors in DMA engine.

Adding AxiRam and its simulation testbed

Description

JIRA

Asynchronous Gearbox

Description

Details

Update for LMK/DAC init sequence for cryo, use pulsed SysRef

Description

Details

JIRA

Related

AxiStream Batcher Version1

Description

Notes

JIRA

Remove AxiStreamPacketizerMux

Description

Rogue device tweaks

Description

Details

Add a generic Gearbox module

Description

Details

Potential uses

Adding inferred RAM support to AxiRam.vhd

Description

I2C Cleanup

Description

Removed AxiI2cMasterCore.

Removed USER register functionality from I2cRegMasterAxiBridge

Add AxiStreamRepeater.vhd

Description

Re-coding axiSlaveRegister to not use recursion

Description

JIRA

Propagate RSSI Segment Size to the Packetizer

Description

Details

JIRA

Related

Depreciating surf.misc.GenericMemory.py

Description

JIRA

Depreciating AxiStreamBatcherEventBuilder's Event Interface

Description

adding SyncTrigPeriod.vhd

Description