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@ruck314 ruck314 released this 05 Mar 21:22
v1.9.7
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Pull Requests

  1. #387 - v1.9.7 release candidate
  2. #376 - Upgrading legacy rogue stream sim wrap
  3. #386 - Add generic boxcar integrator
  4. #380 - Convert simulation receivers to non blocking instead of timeout
  5. #375 - AxiStreamTap.vhd & AxiStreamBatcherEventBuilder.vhd Update
  6. #384 - python/surf/devices/micron/ & MmcmEmulation.vhd update
  7. #377 - AxiVersion.vhd Update
  8. #378 - Update AxiVersion with better use of LinkVariables
  9. #381 - adding StdMatch() fucntion to StdRtlPkg.vhd
  10. #379 - Allow dontcares in AxiLiteCrossbar config
  11. #374 - AxiStreamBatcher.vhd Update
  12. #383 - Remove std_ulogic_vector variant of StdMatch()

Pull Request Details

v1.9.7 release candidate
Author: Larry Ruckman [email protected]
Date: Tue Mar 5 13:21:11 2019 -0800
Pull: #387 (899 additions, 851 deletions, 29 files changed)
Branch: slaclab/pre-release

Notes:

Description

  • Allow dontcares in AxiLiteCrossbar config (#379)
  • Adding StdMatch() fucntion to StdRtlPkg.vhd (#381)
  • Convert simulation receivers to non blocking instead of timeout (#380)
  • Update AxiVersion with better use of LinkVariables (#378)
  • Upgrading legacy rogue stream sim wrap (#376)
  • AxiVersion.vhd Update (#377)
  • AxiStreamTap.vhd & AxiStreamBatcherEventBuilder.vhd Update (#375)
  • AxiStreamBatcher.vhd Update (#374)
  • python/surf/devices/micron/ & MmcmEmulation.vhd update (#384)
  • Add generic boxcar integrator (#386)

Upgrading legacy rogue stream sim wrap
Author: Larry Ruckman [email protected]
Date: Wed Feb 20 08:49:08 2019 -0800
Pull: #376 (127 additions, 384 deletions, 13 files changed)
Branch: slaclab/upgrading-legacy-RogueStreamSimWrap

Notes:

Description

  • adding 256 TDEST support to RogueTcpStreamWrap
  • removing unused sim source code
  • upgrading protocols/pgp/pgp3 to RogueTcpStreamWrap

Add generic boxcar integrator
Author: Larry Ruckman [email protected]
Date: Tue Mar 5 11:55:38 2019 -0800
Pull: #386 (382 additions, 105 deletions, 3 files changed)
Branch: slaclab/generic_integrator

Notes:

This is a generic boxcar integrator which can operate at the full clock rate and supports a configurable integration time.

This includes a test bench which tests changing boxcar sizes and different input valid spacings.

Convert simulation receivers to non blocking instead of timeout
Author: Larry Ruckman [email protected]
Date: Mon Feb 25 16:52:07 2019 -0800
Pull: #380 (84 additions, 112 deletions, 6 files changed)
Branch: slaclab/fix_blocking

Notes:

The previous versions were not doing non-blocking receive calls to the zeromq sockets. Instead they were waiting for a period of time. This was causing simulations to run slow.

AxiStreamTap.vhd & AxiStreamBatcherEventBuilder.vhd Update
Author: Larry Ruckman [email protected]
Date: Tue Feb 19 15:44:31 2019 -0800
Pull: #375 (118 additions, 49 deletions, 2 files changed)
Branch: slaclab/ruckman-dev

Notes:

Description

  • Exposing ILEAVE_ON_NOTVALID_G & ILEAVE_REARB_G in AxiStreamTap.vhd
  • Adding optional timeout feature to AxiStreamBatcherEventBuilder.vhd

python/surf/devices/micron/ & MmcmEmulation.vhd update
Author: Larry Ruckman [email protected]
Date: Tue Mar 5 12:07:55 2019 -0800
Pull: #384 (49 additions, 106 deletions, 4 files changed)
Branch: slaclab/memory-overlap-bug-fix

Notes:

Description

  • Resolved the memory overlaps in python/surf/devices/micron/
  • MmcmEmulation.vhd update

AxiVersion.vhd Update
Author: Larry Ruckman [email protected]
Date: Wed Feb 20 08:37:48 2019 -0800
Pull: #377 (74 additions, 67 deletions, 2 files changed)
Branch: slaclab/AxiVersion-update

Notes:

Description

  • Changing AUTO_RELOAD_TIME_G from real to positive
  • Require for CLK of 250 MHz and 10 sec reload time without going out-of-range of integer (2147483647)

Update AxiVersion with better use of LinkVariables
Author: Benjamin Reese [email protected]
Date: Mon Feb 25 11:31:41 2019 -0800
Pull: #378 (31 additions, 28 deletions, 1 files changed)
Branch: slaclab/ESROGUE-297
Jira: https://jira.slac.stanford.edu/issues/ESROGUE-297

Notes:

This update takes advantage of LinkVariables to parse the buildstring. A hardware read will only be called when the get() method is called on one of the link variables. I also updated the upTime link variable.

adding StdMatch() fucntion to StdRtlPkg.vhd
Author: Larry Ruckman [email protected]
Date: Tue Feb 26 09:22:50 2019 -0800
Pull: #381 (33 additions, 0 deletions, 1 files changed)
Branch: slaclab/std-match

Notes:

Description

adding StdMatch() fucntion to StdRtlPkg.vhd

Allow dontcares in AxiLiteCrossbar config
Author: Larry Ruckman [email protected]
Date: Tue Feb 26 15:13:11 2019 -0800
Pull: #379 (14 additions, 6 deletions, 1 files changed)
Branch: slaclab/axi-xbar

Notes:

This change allows dontcare '-' values for addresses in AxiLiteCrossbar configuration constants.

Description

The AxiLiteCrossbar uses fixed addressing when decoding base addresses. As a consequence, the base address needs to be passed down through generics to any module that instantiates an AxiLiteCrossbar down in the hierarchy. This can be annoying.

This change allows relative addressing when decoding the base address by allowing dontcare values in baseAddr fields.

Example:

constant AXIL_XBAR_CFG_DEFAULT_C : AxiLiteCrossbarMasterConfigArray(0 to 3) := (
      0                  => (
            baseAddr     => X"---00000",
            addrBits     => 16,
            connectivity => X"FFFF"),
      1                  => (
            baseAddr     => X"---10000",
            addrBits     => 16,
            connectivity => X"FFFF"),
      2                  => (
            baseAddr     => X"---20000",
            addrBits     => 16,
            connectivity => X"FFFF"),
      3                  => (
            baseAddr     => X"---30000",
            addrBits     => 16,
            connectivity => X"FFFF"));

Details

This is mostly intended as a stopgap. Using dontcares with hexadecimal formatting means that they always occupy 4 bits each, so base addresses would need to lie of 4-bit boundaries. It works but its not ideal.

Eventually I'd like to rewrite the crossbar config generic with better fields. (We'd get rid of the mostly useless connectivity field too).

AxiStreamBatcher.vhd Update
Author: Larry Ruckman [email protected]
Date: Fri Feb 8 17:37:44 2019 -0800
Pull: #374 (4 additions, 6 deletions, 1 files changed)
Branch: slaclab/AxiStreamBatcher-update

Notes:

Description

  • depreciating lastByteCnt and replacing with WIDTH for SW performance improvement

Note

The revision controlled confluence page got updated today as well:
https://confluence.slac.stanford.edu/display/ppareg/AxiStream+Batcher+Protocol+Version+1

Remove std_ulogic_vector variant of StdMatch()
Author: Benjamin Reese [email protected]
Date: Tue Feb 26 15:14:29 2019 -0800
Pull: #383 (0 additions, 5 deletions, 1 files changed)
Branch: slaclab/std-match

Notes:

Remove a StdMatch overload that was causing a compile error.

Description

This line:

function StdMatch (L, R: std_ulogic_vector) return boolean;

was causing this error:

The following error(s) were detected during synthesis:
 a homograph of stdmatch is already declared in this region [/u/re/bareese/projects/heavy-photon-daq/firmware/submodules/surf/base/general/rtl/StdRtlPkg.vhd:154]
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details

This overloaded StdMatch function has been removed.

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