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@ruck314 ruck314 released this 20 Mar 05:35
v1.9.8
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Pull Requests

  1. #400 - v1.9.8 release candidate
  2. #350 - RSSI Version 1b Release
  3. #382 - Misc. Ethernet Updates
  4. #399 - Clink Development Updates
  5. #385 - AxiDualPortRam & RSSI Update
  6. #402 - More CLink Development Updates
  7. #393 - Updates from CamerLink-Gateway development
  8. #401 - Update XPM wrappers to allow up to 100 READ_LATENCY_G.
  9. #388 - Fix hardReset, softReset and countReset for PGPv2b
  10. #394 - Fix AXI Lite protocol bug in RogueTcpMemory
  11. #403 - Latch integrator output valid
  12. #397 - adding ACK/NAK response detection to ClinkSerialRx.py
  13. #398 - Fix for ADC32RF45 pyrogue
  14. #392 - Enable synchronizer on status bits for TenGigEth Axil registers.
  15. #389 - protocols/pgp/pgp2b/gtp7: Remove partial open port assignments

Pull Request Details

v1.9.8 release candidate
Author: Larry Ruckman [email protected]
Date: Tue Mar 19 22:32:42 2019 -0700
Pull: #400 (5919 additions, 1510 deletions, 121 files changed)
Branch: slaclab/pre-release

Notes:

Description

  • protocols/pgp/pgp2b/gtp7: Remove partial open port assignments (#389)
  • Enable synchronizer on status bits for TenGigEth Axil registers. (#392)
  • Fix hardReset, softReset and countReset for PGPv2b (#388)
  • RSSI Version 1b Release (#350)
  • Updates from CamerLink-Gateway development (#393, #399, #402)
  • Misc. Ethernet Updates (#382)
  • Fix for ADC32RF45 pyrogue (#398)
  • AxiDualPortRam & RSSI Update (#385, #401)
  • Fix AXI Lite protocol bug in RogueTcpMemory (#394)
  • Latch integrator output valid (#403)

RSSI Version 1b Release
Author: Larry Ruckman [email protected]
Date: Fri Mar 8 11:44:09 2019 -0800
Pull: #350 (3385 additions, 17 deletions, 23 files changed)
Branch: slaclab/axi-rssi-dev

Notes:

Description

  • RSSI Version 1b has zero changes to the RSSI Version 1 "protocol" (recycling most of the existin RSSI firmware)
  • This version using an external AXI memory interface for buffering (instead of internal BRAMs)
  • This opens up the possibility to do large (up to 256 segment) buffering via external memory (like DDR)
  • RSSI + PackerV2 = 6.4kLUTs, 6.9kREG, 3 RAMB36, 3 DSP48

Misc. Ethernet Updates
Author: Larry Ruckman [email protected]
Date: Fri Mar 8 14:24:42 2019 -0800
Pull: #382 (558 additions, 768 deletions, 64 files changed)
Branch: slaclab/eth-dev

Notes:

Description

  • In EthMacTxExportXgmii.vhd: Optimized 'Layer 2 Ethernet frame' min size from 72 octets to 65 octets (64 octets is the limit with respect to IEEE 802.3)
  • Overhauled the EthMacTb.vhd to do a byte sweep from 16 octets to 260 octets to test for zero padding implementation and all byte level corner cases in the XGMII TX export and XGMII RX export
  • Overhauled the UdpEngineTb.vhd to sweep through different PRBS sizes
  • misc ruckus.tcl updates

Clink Development Updates
Author: Larry Ruckman [email protected]
Date: Thu Mar 14 16:01:53 2019 -0700
Pull: #399 (886 additions, 363 deletions, 14 files changed)
Branch: slaclab/ClinkSerialRx-update

Notes:

Description

  • adding rstPll and rstFsm commands
  • changing ClinkData.REG_INIT_C.delay to zero
  • execute ResetFsm() after YAML load automatically
  • adding Blowoff debugging register

AxiDualPortRam & RSSI Update
Author: Larry Ruckman [email protected]
Date: Tue Mar 12 15:43:04 2019 -0700
Pull: #385 (514 additions, 191 deletions, 13 files changed)
Branch: slaclab/AxiDualPortRam-update

Notes:

Description

  • Adding URAM support toAxiDualPortRam & RSSI for Ultrascale+

More CLink Development Updates
Author: Larry Ruckman [email protected]
Date: Mon Mar 18 10:17:49 2019 -0700
Pull: #402 (337 additions, 170 deletions, 7 files changed)
Branch: slaclab/ClinkSerialRx-update

Notes:

Description

  • adding soft/hard resets to AxiStreamBatcherEventBuilder.vhd
  • adding cntRst and lockCnt status counters
  • removed r.byteData.lv = 0x0 condition from dropFrame

Updates from CamerLink-Gateway development
Author: Larry Ruckman [email protected]
Date: Fri Mar 8 14:22:57 2019 -0800
Pull: #393 (230 additions, 22 deletions, 8 files changed)
Branch: slaclab/clink-dev

Notes:

Description

  • fixed memory overlap in AxiStreamMonitoring.py
  • updating AxiVersion.py print out (useful when you have more than 1 AxiVersion in your SW)
  • prevent CLink bandrate of zero
  • updating ClinkChannel.py
  • adding AxiStreamBatcherEventBuilder.py
  • bug fix for AxiStreamBatcherEventBuilder.vhd when r.timeout /= 0

Update XPM wrappers to allow up to 100 READ_LATENCY_G.
Author: Larry Ruckman [email protected]
Date: Mon Mar 18 10:20:10 2019 -0700
Pull: #401 (35 additions, 17 deletions, 5 files changed)
Branch: slaclab/xpm-mem-dev

Notes:

Description

Update XPM wrappers to allow up to 100 READ_LATENCY_G.
Update AxiDualPortRamp to allow up to READ_LATENCY = 3

Fix hardReset, softReset and countReset for PGPv2b
Author: Benjamin Reese [email protected]
Date: Fri Mar 8 11:37:37 2019 -0800
Pull: #388 (12 additions, 10 deletions, 1 files changed)
Branch: slaclab/pgp-rogue-fix

Notes:

Description

The Device was defining hardReset, softReset and countReset functions in the constructor. These need to be methods.

Fix AXI Lite protocol bug in RogueTcpMemory
Author: Benjamin Reese [email protected]
Date: Thu Mar 14 20:47:11 2019 -0700
Pull: #394 (10 additions, 8 deletions, 1 files changed)
Branch: slaclab/tcp-memory-fix

Notes:

Description

Fixed a bug in RogueTcpMemory.c that caused to it start the next transaction before the bus was ready.

Details

Master bus needs to wait for BVALID / RVALID to go low in response to BREADY / RREADY before starting the next transaction.

Note

I haven't verified that writes work yet.

Latch integrator output valid
Author: Larry Ruckman [email protected]
Date: Tue Mar 19 22:23:21 2019 -0700
Pull: #403 (11 additions, 6 deletions, 1 files changed)
Branch: slaclab/update_boxcar

Notes:

This allows the integrator to run in a mode where the putput valid is held until acked. The ack signal does not act as flow control.

adding ACK/NAK response detection to ClinkSerialRx.py
Author: Larry Ruckman [email protected]
Date: Mon Mar 11 21:57:15 2019 -0700
Pull: #397 (6 additions, 1 deletions, 1 files changed)
Branch: slaclab/ClinkSerialRx-update

Notes:

Description

  • adding ACK/NAK response detection to ClinkSerialRx.py

Fix for ADC32RF45 pyrogue
Author: Larry Ruckman [email protected]
Date: Tue Mar 12 15:27:37 2019 -0700
Pull: #398 (1 additions, 1 deletions, 1 files changed)
Branch: slaclab/cryo-pyrogue-fix

Notes:

Description

Fix pyrogue for Adc32Rf45

Enable synchronizer on status bits for TenGigEth Axil registers.
Author: Larry Ruckman [email protected]
Date: Wed Mar 6 15:39:50 2019 -0800
Pull: #392 (1 additions, 1 deletions, 1 files changed)
Branch: slaclab/tenGigEthRegSynchronizer

Notes:

Description

The TenGigEthReg module feature a synchronizer for status bits which are read
into AXIL registers. The module assumes that all status bits originate in the
same clock domain as the module itself and disables the synchronizer.

However, there are some bits which originate in a different clock domain. This
PR simply enables the (already coded) synchronizer.

Details

Some of the status bits:

gtTxRst,
gtRxRst,
rstCntDone,
rxRstdone,
txRstdone

are not generated in the target clock domain (phyClk).
Probably not that critical, but nevertheless...

(bits 17, 16, 12, 13, 14)

protocols/pgp/pgp2b/gtp7: Remove partial open port assignments
Author: Benjamin Reese [email protected]
Date: Wed Mar 6 09:15:50 2019 -0800
Pull: #389 (0 additions, 2 deletions, 2 files changed)
Branch: slaclab/hps-dev

Notes:

Description

Remove partial open port vector assignments.

Details

VHDL technically doesn't allow vector port assignments where one index is assigned to open. VCS complains about this. This PR removes to such assignments in pgp2b/gtp7.

There are a whole bunch of commits because this was a development branch for a project, but everything else has already been merged and this small change is all that's left at the moment.

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