fix to cache due to mismatch of bram model btw hardware and sim

sylefeb · Oct 27, 2023 · 05612f8 · 05612f8
1 parent 8c47f4e
commit 05612f8
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Showing 2 changed files with 25 additions and 8 deletions.
diff --git a/projects/common/qpsram2x.si b/projects/common/qpsram2x.si
@@ -208,6 +208,8 @@ $$end
         vdta.wdata              = wdata;
         vdta.wenable            = wenable & continue;
         vdta.addr               = vdta.addr + 1;
+  $$elseif ICARUS then
+        rdata                   = cycle[0,8];
   $$else
         rdata                   = spi.read;
   $$end

diff --git a/projects/ice-v/SOCs/swirl-cache.si b/projects/ice-v/SOCs/swirl-cache.si
@@ -18,6 +18,9 @@
 // https://github.com/sylefeb/Silice
 // MIT license, see LICENSE_MIT in Silice repo root
 
+/// TODO: write needs to be rechecked for the 2x case (latency on reg_ram_datanext)
+///       (first value may be incorrect?)
+
 // from the outside the cache acts as a BRAM when filled
 interface bram_provider
 {
@@ -102,13 +105,15 @@ $$end
     ram_io0 <:> ram_io0,    ram_io1 <:> ram_io1,
     ram_io2 <:> ram_io2,    ram_io3 <:> ram_io3,
   );
+  adapt_data_next adapt<@clock2x>(data_next_2x <: ram.data_next,
+                                  rdata_2x     <: ram.rdata);
   uint1 reg_ram_datanext(0);
-  adapt_data_next _<@clock2x>(data_next_2x <: ram.data_next, data_next :> reg_ram_datanext);
   uint8 reg_ram_rdata(0);
 
   uint1 update_lines_todo(0);
   uint1 update_lines_done(0);
   uint1 write_cycle(0);
+  uint1 keep_wait(0);
 
   always_before {
 /*
@@ -148,9 +153,10 @@ $$end
     spram2.data_in       = mem1.wdata[ 0,16];
     spram3.data_in       = mem1.wdata[16,16];
     // if both caches missed, raise wait
-    wait                 = reset | ~cache0_hit | ~cache1_hit | write_cycle;
+    wait                 = reset | ~cache0_hit | ~cache1_hit | write_cycle | keep_wait;
     //                     ^^^^^ wait during reset too         ^^^^^^^^^^^
     write_cycle          = 0; // additional cycle for writes, after an update
+    keep_wait            = 0; // see note where set
     //if (~cache0_hit | ~cache1_hit) {
     //  __display("[%d] >> cache miss %b|%b %x|%x",cycle,~cache0_hit,~cache1_hit,qaddr0<<2,qaddr1<<2);
     //}
@@ -197,7 +203,7 @@ $$end
                         ? {spram1.data_out,spram0.data_out} >> {n[0,2],3b0}
                         : {spram3.data_out,spram2.data_out} >> {n[0,2],3b0};
             // next?
-            if (reg_ram_datanext) {
+            if (reg_ram_datanext) { ///////// CHECK: too much latency due to reg?
               //__write("%x,",ram.wdata);
               // next
               n = n + 1;
@@ -263,9 +269,14 @@ $$end
           cache1_lines.wdata   = {1b0,qaddr1[$cache_line_width$,$cache_addr_w$]};
           cache1_lines.wenable = 1;
         }
+        keep_wait         = 1; // IMPORTANT: keeps wait high during bram transaction
+                               // otherwise results depends on bram read-on-write
+                               // behavior
+                               // NOTE: simply keep wait high while loop active?
 ++:     // wait for cache lines bram to be written
         update_lines_done = 1; // done
-        write_cycle       = 1; // TODO: only if indeed writing ...
+        write_cycle       = 1; // keeps wait high while write to cache line occurs
+                               // TODO: only if indeed writing?
 $$if SIMULATION then
         __display("[%d] cache done.",cycle);
 $$end
@@ -290,7 +301,8 @@ $$end
     qaddr0    = mem0.addr;    qaddr1    = mem1.addr;
     qwen0     = mem0.wenable; qwen1     = mem1.wenable;
     // cross clock domain
-    reg_ram_rdata    = ram.rdata;
+    reg_ram_datanext = adapt.data_next;
+    reg_ram_rdata    = adapt.rdata;
     /*
     __display("[%d] >> cache status out: @%x|@%x q: @%x|@%x miss: %b|%b ln: %x|%x ln@: %x|%x  lnw: %b|%b",
                 cycle,mem0.addr<<2,mem1.addr<<2,
@@ -314,12 +326,15 @@ $$end
 // - should run at 2x
 // --------------------------------------------------
 
-unit adapt_data_next(input uint1 data_next_2x, output uint1 data_next)
+unit adapt_data_next(
+  input uint1 data_next_2x,  output uint1 data_next,
+  input uint8 rdata_2x,      output uint8 rdata)
 {
   uint2 dnext(0);
   always {
-    dnext     = data_next_2x ? 2b11 : {1b0,dnext[1,1]};
-    data_next = dnext[0,1];
+    dnext      = data_next_2x ? 2b11 : {1b0,dnext[1,1]};
+    data_next  = dnext[0,1];
+    rdata      = rdata_2x;
   }
 }