A compilation of the different ways Yosys can be used to aid with RTL design

Name		Name	Last commit message	Last commit date
Latest commit History 23 Commits
FSM diagram		FSM diagram
Generate a schematic of RTL using GTECH symbols		Generate a schematic of RTL using GTECH symbols
A guide to logic synthesis using Yosys.pdf		A guide to logic synthesis using Yosys.pdf
README.md		README.md

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