Xtensa patches (19.x) (Do not merge, PR created for easier review only) #109

gerekon · 2025-01-14T16:37:23Z

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…Dag. Remove SHL/SRL/SRA/SRC pseudo operations. Remove redundant cttz/ctlz/ctpop tests. Remove Xtensa MachineFunctionInfo implementation.

…ns selection.

Add support for llvm.{frameaddress,returnaddress} intrinsics.

Implement volatile load/store from/to volatile memory location.

Also implement User Registers class.

Implement DAG Combine for BRCOND operation with f32 operands.

Implement Debug, DFPAccel, S32C1I, THREADPTR, Extended L32R, ATOMCTL, MEMCTL features.

Implement Exception, HighPriInterrupts, Coprocessor, Interrupt, RelocatableVector, TimerInt, PRID, RegionProtection and MiscSR features. Implement instructions for Exception, Interrupt and RegionProtection features with tests.

Make ESP32 default subtarget.

Implement subtarget dependent SR and UR register parsing and disassembling, add tests. Implement User Registers read/write instructions and add tests.

…tros

It was changed in LLVM 18

andreisfr added 30 commits October 17, 2024 10:00

[Xtensa] Move SHL/SRL/SRA/SRC lowering from ISelLowering to ISelDagTo…

f810f79

…Dag. Remove SHL/SRL/SRA/SRC pseudo operations. Remove redundant cttz/ctlz/ctpop tests. Remove Xtensa MachineFunctionInfo implementation.

[Xtensa] Minor fixes

0414d44

[Xtensa] Imrpove CTPOP lowering. Minor fixes int SHL/SRC/SRA operatio…

f05cf16

…ns selection.

[Xtensa] Fix shift tests.

a860cda

[Xtensa] Implement load pseudo operations and patterns.

87c8d07

[Xtensa] Support for variable arguments

ab3e8ed

[Xtensa] Add support for address intrinsics.

38fd8e9

Add support for llvm.{frameaddress,returnaddress} intrinsics.

[Xtensa] Add basic support for inline asm constraints

2d780d8

[Xtensa] Implement volatile load/store.

ef77b89

Implement volatile load/store from/to volatile memory location.

[Xtensa] Implement branch analysis

1903a38

[Xtensa] Implement support for the BranchRelaxation

36cf87e

[Xtensa] Implement code density feature operations

e525aee

[Xtensa] Add code size reduction pass.

f48a873

[Xtensa] Implement Windowed feature operations

c9cd06d

[Xtensa] Implement Windowed Call ABI.

4c5483f

[Xtensa] Fix reserving of the emergency spill slot.

3b8e821

[Xtensa] Implement Boolean feature operations

857dba2

[Xtensa] Implement Floating-Point feature operations.

69c4683

Also implement User Registers class.

[Xtensa] Lowering Floating-Point Operations SELECT_CC/SETCC/BR_CC.

549baa7

Implement DAG Combine for BRCOND operation with f32 operands.

[Xtensa] Implement DAG Combine for FADD and FSUB operations.

6aabafc

[Xtensa] Implement Loop, SEXT and NSA features.

5115e3e

[Xtensa] Implement Mul32, Mul32High and Div32 features.

d34a888

[Xtensa] Implement Mac16 feature and operations.

403ab84

[Xtensa] Implement Xtensa features and operations.

66c182a

Implement Debug, DFPAccel, S32C1I, THREADPTR, Extended L32R, ATOMCTL, MEMCTL features.

[Xtensa] Implement Xtensa features and operations.

b30f4ab

Implement Exception, HighPriInterrupts, Coprocessor, Interrupt, RelocatableVector, TimerInt, PRID, RegionProtection and MiscSR features. Implement instructions for Exception, Interrupt and RegionProtection features with tests.

[Xtensa] Add the Xtensa target.

967c0d0

[Xtensa] Implement Xtensa ABI lowering.

b72a9de

[Xtensa] Add subtargets ESP32. ESP8266 and ESP32-S2.

78cec6f

Make ESP32 default subtarget.

[Xtensa] Add esp32, esp8266 and esp32-s2 to valid cpu names.

6105f48

[Xtensa] Improve parsing of the SR and UR registers.

320130a

Implement subtarget dependent SR and UR register parsing and disassembling, add tests. Implement User Registers read/write instructions and add tests.

gerekon and others added 29 commits October 17, 2024 10:01

[LLVM][Xtensa] Remove DFP accelrator feature from ESP32-S3

7d821ec

[Clang][Xtensa] Add tests for core config pre-defined macros

1d54b93

esp/ci: Upgrade GCC toolchain components version to '13.2.0_20240305'

69dbc78

[Clang][RISCV] Fix baremetal test

b720717

[Toolchain][Espressif] Use custom prefixes for 'as' and 'ld'

19d06ae

esp/ci: Switch to combined all-in-one toolchain

76de474

esp/ci: Add special build to run tests

337b1fc

[Xtensa] Fix LOOP* pseudo instructions.

443eac0

esp/ci: Upgrade docker image for Windows build to use MinGW 10

93a4e7d

[Xtensa] Fix issue with adding scavenging frame index

2cc4c57

esp/ci: Separate checksum files for toolchain and standalone libs dis…

c7d3e98

…tros

[RISCV] Add user trap CSRs

052f6cf

[Xtensa] Add Xtensa builtins into last builtin ID calculation

730507e

[Xtensa] Support for asm underscore prefix

e112a97

[Clang][Xtensa] Improve esp baremetal toolchain. Fix tests.

d34fe2f

[Xtensa] Fix atomic store operands order

acc3019

It was changed in LLVM 18

toolchain/esp: Add test for 'xesppie' multilib mapping for esp32-p4

e58e877

[Clang][Xtensa] Fix Espressif baremetal toolchain tests.

277220c

[Xtensa][Test] Fix xtensa-ee-intrinsics test

c352401

[RISCV] Support for ESP32-P4 instructions in RISCV backend.

fd1c569

[Xtensa] Fix lowering BRCOND.

031fa7b

[Xtensa] Fix lowering SELECT_CC and SETCC.

296f186

[Xtensa] Fix lowering ConstantPool.

1ba66c2

[Xtensa] Fix lowering immediate.

caf476f

[Xtensa] Fix emitting literals section.

aa12798

[Xtensa][Test] Fix compiler-rt test config.

e5e3894

esp/ci: Fix git dubious ownership error

a01719f

esp/ci: Use build script repo LLVM 19 release branch

54186c4

esp/ci: Update docker images for LLVM 19 release

46050f3

gerekon mentioned this pull request Jan 14, 2025

Xtensa patches (18.x) (Do not merge, PR created for easier review only) #94

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Xtensa patches (19.x) (Do not merge, PR created for easier review only) #109

Xtensa patches (19.x) (Do not merge, PR created for easier review only) #109

gerekon commented Jan 14, 2025

Xtensa patches (19.x) (Do not merge, PR created for easier review only) #109

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Xtensa patches (19.x) (Do not merge, PR created for easier review only) #109

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gerekon commented Jan 14, 2025