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Add riscv-rt to workspace #151

Merged
merged 314 commits into from
Nov 27, 2023
Merged

Add riscv-rt to workspace #151

merged 314 commits into from
Nov 27, 2023

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romancardenas
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This PR adds riscv-rt to this workspace. I'm still working on fine-tuning the CI, let me know your opinion and I'll push it to the PR 😄

Disasm and others added 30 commits March 5, 2019 18:06
@Disasm
Regenerate binaries
465690e
@Disasm
Update 'riscv' dependency
b7dac85
@bors @Disasm
Merge #28
099033f 
28: Add support for 64-bit targets r=dvc94ch a=Disasm



Co-authored-by: Vadim Kaushan <[email protected]>
@Disasm
Copy cortex-m-rt-macros
06e1528
@Disasm
[macros] Fix Cargo.toml
85efa3b
@Disasm
[macros] Replace cortex-m with riscv
1ad79f8
@Disasm
Use proc-macro entry
f981ee6
@Disasm
Add 'pre_init' attribute
f11f052
@Disasm
[macros] Remove 'static mut' hack
253aa88
@Disasm
[macros] Remove 'exception' and 'interrupt' attributes
64fb6ad
@bors @Disasm
Merge #27
816b3ce 
27: Add 'entry' and 'pre_init' attributes r=dvc94ch a=Disasm

Implementation is based on [`cortex-m-rt-macros`](https://github.com/rust-embedded/cortex-m-rt/tree/master/macros) code.

This implementation has been changed to make `static mut` unsafe inside entry point and different handlers.

Related: rust-embedded/riscv-rt#20

Co-authored-by: Vadim Kaushan <[email protected]>
@Disasm
Fix documentation
d2eff45
@Disasm
Add MSRV policy
f572fde
@Disasm
Bump version
e85c1fb
@bors @Disasm
Merge #30
fdc92f3 
30: Fix docs, add MSRV policy, bump version r=dvc94ch a=Disasm



Co-authored-by: Vadim Kaushan <[email protected]>
@Disasm
Produce a compilation error if riscv-rt appears more than once in the…
8163823 
… dependency graph
@Disasm
Update 'riscv' dependency
1c716aa
@Disasm
Initialize FPU when available
373d773
@Disasm
Fix linker script: produce correct program headers
a4ac2f3
@Disasm
Fix _stext redefinition
43b527c
@Disasm
Use region aliases in the linker script
fdd627d
@Disasm
Put provides in one place
ec35554
@Disasm
Add more asserts
9d64f83
@Disasm
Allocate stacks for all the harts
b04261e
@Disasm
Turn abort() into an infinite loop
c4d4b7a
@Disasm
Set stack pointer for all the harts
b50b9ed
@Disasm
Revert "Initialize FPU when available"
c201a96 
This reverts commit 373d773.
@Disasm
Initialize GPR and MSR state
73e56eb
@Disasm
Set frame pointer right after stack allocation
1f9677f
@Disasm
Set trap handler in assembly
03f4eef
MabezDev and others added 16 commits October 3, 2023 21:10
@MabezDev
Merge pull request #125 from rust-embedded/label-patch
ea1deea 
Remove label-check from merge_group
@romancardenas
build.rs now adapts link.x for the target arch
b84edd6
@kevin-vigor
Ignore hartid in single-hart mode.
0631b3a 
Don't bother checking hart ID on startup in single-hart mode. Allows
use of cores with unusual mhartid values and saves a few instructions.
@romancardenas
Merge pull request #126 from kevin-vigor/master
448eec9 
Ignore hartid in single-hart mode.
@ivq
Fix setting incorrect sp if single-hart
1a22ec5 
If single-hart is enabled, the sp is set to _stack_start - _hart_stack_size,
rather than _stack_start. Fix this.

Fixes: e540f1e ("Add feature single-hart")
Signed-off-by: Chien Wong <[email protected]>
@ivq
Add 'single-hart' changelog entry
17185e9 
Signed-off-by: Chien Wong <[email protected]>
@ivq
Update doc on single-hart
408acae 
Signed-off-by: Chien Wong <[email protected]>
@romancardenas
Merge pull request #128 from ivq/fix_single_hart_stack
34e07c6 
Fix setting incorrect sp if single-hart
@ivq
Ensure sp is 16-byte aligned
b737208 
Signed-off-by: Chien Wong <[email protected]>
@romancardenas
Merge pull request #129 from ivq/sp_align
0383469 
Ensure sp is 16-byte aligned
@romancardenas
Merge branch 'master' into new_build
f2b1dea
@MabezDev
Merge pull request #127 from rust-embedded/new_build
721f107 
build.rs now adapts link.x for the target arch
@romancardenas
Merge remote-tracking branch 'riscv-rt/master' into add-riscv-rt
0bae216
@romancardenas
Setting CI (WIP)
cd474dd
@romancardenas
fix build.yaml
612d58d
@romancardenas
separation of CI
edf4dac
@romancardenas romancardenas added the do not merge this code should not be merged to master label Nov 17, 2023
@romancardenas romancardenas requested a review from a team as a code owner November 17, 2023 15:16
@romancardenas romancardenas removed the do not merge this code should not be merged to master label Nov 20, 2023
@romancardenas
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@rust-embedded/riscv good to go! Take a look and let me know if I forgot something

jessebraham
jessebraham requested changes Nov 27, 2023
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Few little nitpicks but otherwise LGTM!

riscv-rt/README.md Outdated Show resolved Hide resolved
riscv-rt/macros/Cargo.toml Outdated Show resolved Hide resolved
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@romancardenas
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Thanks for your review @jessebraham ! I addressed all your comments and adapted the general README.md file from cortex-m

jessebraham
jessebraham approved these changes Nov 27, 2023
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Thanks for making those changes, LGTM!

@romancardenas romancardenas added this pull request to the merge queue Nov 27, 2023
Merged via the queue into master with commit f8c3923 Nov 27, 2023
58 checks passed
@romancardenas romancardenas deleted the add-riscv-rt branch November 27, 2023 17:02
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