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Add riscv-rt to workspace #151

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merged 314 commits into from
Nov 27, 2023
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465690e
Regenerate binaries
Disasm Mar 5, 2019
b7dac85
Update 'riscv' dependency
Disasm Mar 5, 2019
099033f
Merge #28
bors[bot] Mar 5, 2019
06e1528
Copy cortex-m-rt-macros
Disasm Mar 5, 2019
85efa3b
[macros] Fix Cargo.toml
Disasm Mar 5, 2019
1ad79f8
[macros] Replace cortex-m with riscv
Disasm Mar 5, 2019
f981ee6
Use proc-macro `entry`
Disasm Mar 5, 2019
f11f052
Add 'pre_init' attribute
Disasm Mar 5, 2019
253aa88
[macros] Remove 'static mut' hack
Disasm Mar 5, 2019
64fb6ad
[macros] Remove 'exception' and 'interrupt' attributes
Disasm Mar 5, 2019
816b3ce
Merge #27
bors[bot] Mar 7, 2019
d2eff45
Fix documentation
Disasm Mar 7, 2019
f572fde
Add MSRV policy
Disasm Mar 7, 2019
e85c1fb
Bump version
Disasm Mar 7, 2019
fdc92f3
Merge #30
bors[bot] Mar 11, 2019
8163823
Produce a compilation error if riscv-rt appears more than once in the…
Disasm Mar 15, 2019
1c716aa
Update 'riscv' dependency
Disasm Mar 29, 2019
373d773
Initialize FPU when available
Disasm Mar 29, 2019
a4ac2f3
Fix linker script: produce correct program headers
Disasm Apr 1, 2019
43b527c
Fix _stext redefinition
Disasm Apr 1, 2019
fdd627d
Use region aliases in the linker script
Disasm Apr 1, 2019
ec35554
Put provides in one place
Disasm Apr 1, 2019
9d64f83
Add more asserts
Disasm Apr 1, 2019
b04261e
Allocate stacks for all the harts
Disasm Apr 1, 2019
c4d4b7a
Turn abort() into an infinite loop
Disasm Apr 1, 2019
b50b9ed
Set stack pointer for all the harts
Disasm Apr 1, 2019
c201a96
Revert "Initialize FPU when available"
Disasm Apr 9, 2019
73e56eb
Initialize GPR and MSR state
Disasm Apr 28, 2019
1f9677f
Set frame pointer right after stack allocation
Disasm Apr 28, 2019
03f4eef
Set trap handler in assembly
Disasm Apr 28, 2019
84042d7
Do not set mideleg and medeleg (not supported on FE310)
Disasm May 20, 2019
5c1bbc6
Introduce _mp_hook
Disasm May 22, 2019
5d8f8c3
Regenerate binaries
Disasm May 22, 2019
6d14411
Update documentation
Disasm May 22, 2019
0049fd0
Add examples
Disasm May 22, 2019
cf8c9f2
Check examples in CI
Disasm May 22, 2019
984a63d
[macros] Remove riscv-rt dependency
Disasm May 22, 2019
f433e3d
[macros] Bump version (0.1.6)
Disasm May 22, 2019
9685940
Update riscv-rt-macros dependency
Disasm May 22, 2019
15fe992
Bump version (0.6.0)
Disasm May 22, 2019
73f1a1e
Rename RISCV to RISC-V
Disasm May 25, 2019
e336375
Fix build
Disasm Jul 1, 2019
4bdbe78
Merge #32
bors[bot] Jul 2, 2019
b66f595
Merge #31
bors[bot] Jul 2, 2019
eb00f87
Add .sbss section to linker script
laanwj Jul 18, 2019
80759f2
Merge #35
bors[bot] Jul 18, 2019
98f7b1a
Use ALIGN attributes properly
Disasm Jul 19, 2019
8407973
Add .sdata section to linker script
Disasm Jul 19, 2019
03a3639
Fix .data alignment issue
Disasm Jul 19, 2019
8f3ff84
Fix section flags
Disasm Jul 19, 2019
44c86e2
Fix _stext override issue
Disasm Jul 19, 2019
1839103
Add support for 64-bit registers in _start_trap
Disasm Jul 19, 2019
6fe10d1
Regenerate binaries
Disasm Jul 19, 2019
c284f35
Merge #36
bors[bot] Jul 23, 2019
0427294
Merge #37
bors[bot] Jul 23, 2019
370700c
link.x: Add .sdata2 sections
laanwj Aug 7, 2019
e962e8c
Bump version from 0.6.0 to 0.6.1
laanwj Aug 8, 2019
c757933
Merge #38
bors[bot] Aug 8, 2019
cd995c6
Simple typo fix
iankronquist Oct 3, 2019
888a763
Merge #40
bors[bot] Oct 3, 2019
4e9aa15
Make linker script compatible with GNU linker.
pftbest Nov 21, 2019
5a31ab7
Merge #41
bors[bot] Nov 22, 2019
09b1f01
Place abort in the .text section
istankovic Feb 17, 2020
0f39348
Update binaries
istankovic Feb 18, 2020
cd419ae
Merge #43
bors[bot] Feb 19, 2020
23605f5
Assure address of PC at startup.
elfmimi Feb 27, 2020
7e4c1b9
Update binaries
Disasm Feb 27, 2020
c33a988
Merge #46
bors[bot] Feb 28, 2020
f956817
Pass trap frame pointer to the _start_trap_rust function
Disasm Feb 1, 2020
063c009
Regenerate binaries
Disasm Feb 1, 2020
f233381
Implement interrupt and exception handling
Disasm Feb 1, 2020
45c729e
Remove #![deny(warnings)] (anti-pattern)
Disasm Feb 1, 2020
4b68b0f
Merge #42
bors[bot] Feb 29, 2020
579f68d
Replace mul instruction with a loop for rv32i
Disasm Feb 26, 2020
88f0e91
Remove asm.h
Disasm Feb 26, 2020
b729dbf
Add support for riscv32i
Disasm Feb 26, 2020
abd84cc
Generate debug info
Disasm Feb 26, 2020
d771a9e
Regenerate binaries
Disasm Feb 26, 2020
ef6d9e7
Add assemble.ps1
Disasm Mar 7, 2020
bdaeb8e
Use riscv64-unknown-elf-ar in assemble.sh
Disasm Mar 7, 2020
9c172da
Update dependencies
Disasm Mar 7, 2020
d748c84
[CI] allow 64-bit targets on stable
Disasm Mar 7, 2020
c00efce
[CI] Remove obsolete hack
Disasm Mar 7, 2020
05073ff
[CI] Check riscv32i-unknown-none-elf target
Disasm Mar 7, 2020
ab9cccc
Set MSRV to 1.38
Disasm Mar 7, 2020
a2f509e
Merge #45
bors[bot] Mar 10, 2020
5343baf
Add CHANGELOG.md
Disasm Mar 10, 2020
4fc49a4
Release v0.7.0
Disasm Mar 10, 2020
fc79de9
Merge #48
bors[bot] Mar 10, 2020
9cfcd27
Document MSRV on README
eldruin Apr 21, 2020
642ef29
Update CI scripts
Disasm Apr 21, 2020
9c492da
Allow nightly build to fail
Disasm Apr 21, 2020
4ea6ec4
Check blobs in a separate target
Disasm Apr 21, 2020
7ef035a
Merge #50
bors[bot] Apr 21, 2020
e8918a7
Enable gcc caching
Disasm Apr 21, 2020
b67cb52
Only checking for necessary extensions when linking, made debug infor…
ilya-epifanov May 15, 2020
12fb268
fixed the assemble.ps1 PowerShell™ script
ilya-epifanov May 15, 2020
f0afce4
Merge #51
bors[bot] May 16, 2020
0739b22
Merge #52
bors[bot] May 16, 2020
c255c0c
fix rust fmt to not mangle externs
almindor May 16, 2020
80343ad
Merge #53
bors[bot] May 17, 2020
ef768fb
Check code style on CI
Disasm May 17, 2020
ba85a0e
Merge #54
bors[bot] May 17, 2020
48cc1ec
Exception handler may return
laanwj Jun 1, 2020
158d964
Merge #56
bors[bot] Jun 1, 2020
7638761
Surround use of absolute offset with "norelax"
laanwj Jun 1, 2020
ced1ad4
Regenerate binaries
laanwj Jun 1, 2020
8ec323b
Merge #57
bors[bot] Jun 1, 2020
ff86cd0
Add hook to initialize custom interrupt controllers.
khrs Jun 2, 2020
f09f454
Make default_setup_interrupts global
khrs Jun 2, 2020
d1e0564
Update asm.S
khrs Jun 2, 2020
67f67f0
Remove duplicated .global from default_setup_interrupts
khrs Jun 2, 2020
9275ca9
Add doc to PROVIDE.
khrs Jun 2, 2020
3047813
Document .weak usage.
khrs Jun 2, 2020
73ba258
Regenerate BLOBs
khrs Jun 2, 2020
4f09eda
Update CHANGELOG.md
khrs Jun 2, 2020
6f4a9d4
Merge #58
bors[bot] Jun 2, 2020
ed6c4ae
Release v0.7.1
khrs Jun 2, 2020
f1ef3b4
Update CHANGELOG.md
khrs Jun 2, 2020
13744d9
Fix format.
khrs Jun 2, 2020
9f1892e
Merge #59
bors[bot] Jun 2, 2020
2880a75
Preserve .eh_frame and .eh_frame_hdr
Disasm Jul 15, 2020
48d45c3
Add change log entry
Disasm Jul 15, 2020
db65c40
Merge #62
bors[bot] Jul 15, 2020
a9a3fa4
Update link.x
richardeoin Jul 15, 2020
4a89d18
Merge #61
bors[bot] Jul 15, 2020
712433d
Release v0.7.2
Disasm Jul 15, 2020
1d28064
Merge #63
bors[bot] Jul 16, 2020
47416ae
Update riscv dependency to version 0.6
luojia65 Jul 18, 2020
1a1729f
Merge #65
bors[bot] Jul 18, 2020
4e372a8
Release v0.8.0
Disasm Jul 18, 2020
5bfbb27
Merge #66
bors[bot] Jul 18, 2020
ed55f39
Update dependencies of riscv-rt-macros
Disasm Aug 2, 2020
49c1484
Merge #67
bors[bot] Aug 2, 2020
ad9bed1
Fix link to RISC-V team in wg repo
hasheddan Mar 6, 2021
2042f3b
[NFC] Fix typo 'suppoted' -> 'supported'
jmerdich Jun 26, 2021
2f131cd
switch to Github Actions for CI
almindor Jul 19, 2021
b5fcd72
Merge #76
bors[bot] Jul 19, 2021
27c91a0
Merge #73
bors[bot] Jul 19, 2021
acba973
Merge #74
bors[bot] Jul 19, 2021
9a19021
use --target for CI checks
almindor Jul 20, 2021
142f91d
Merge #77
bors[bot] Jul 20, 2021
27b0ed5
update to riscv 0.7
smsxgli Sep 18, 2021
629737e
Merge #79
bors[bot] Sep 19, 2021
daeaf18
Trap handler override improvments
MabezDev Nov 5, 2021
5137b0a
Merge #81
bors[bot] Nov 10, 2021
f1f3b63
Update CHANGELOG.md
parkero Jan 25, 2022
66f5d1f
Merge #86
bors[bot] Jan 25, 2022
6aadc50
release v0.8.1
almindor Jan 26, 2022
5118a29
Merge #87
bors[bot] Jan 26, 2022
3c68180
Update riscv to 0.8 and remove inline-asm feature
taiki-e Apr 23, 2022
76dc8db
Merge #88
bors[bot] Apr 23, 2022
ab70e9f
Fix links in changelog
Disasm Apr 23, 2022
5fcb5ef
Update copyright years
Disasm Apr 23, 2022
98eba1d
Merge #89
bors[bot] Apr 23, 2022
8bae02e
Merge #90
bors[bot] Apr 26, 2022
5c8b061
Don't use a random hash ident, instead use the crate prefixed symbol.
MabezDev Jun 10, 2022
3f7e297
Merge #91
bors[bot] Jun 10, 2022
63a9486
Use std::fs::write in build.rs
SimonSapin Jun 23, 2022
89c97b4
cargo:rerun-if-changed=build.rs is redundant
SimonSapin Jun 23, 2022
3c50674
Printing cargo:rustc-link-search=$OUT_DIR twice is redundant
SimonSapin Jun 23, 2022
17e0aa2
Rerun the build script if the bin/{}.a archive has changed
SimonSapin Jun 23, 2022
6bd66a2
Merge #93
bors[bot] Jun 23, 2022
57219ef
Pass a0..a2 to main()
Disasm Jun 25, 2022
4b98bd4
Merge #95
bors[bot] Jun 29, 2022
61aaa6c
Add missing changelog entries
Disasm Jun 30, 2022
259d1ca
Merge #96
bors[bot] Jun 30, 2022
55b830d
Release v0.9.0
Disasm Jul 1, 2022
cf962d8
Merge #97
bors[bot] Jul 1, 2022
01097fd
Convert default_setup_interrupts into a Rust function
Disasm Jul 3, 2022
29e1590
Merge #98
bors[bot] Jul 3, 2022
dd23217
Simplify build.rs example
Disasm Jul 11, 2022
9e7d5a0
Merge #100
bors[bot] Jul 11, 2022
b89b4e4
Remove superfluous parentheses from link.x
jannic Sep 8, 2022
c5f355d
Add CHANGELOG entry
jannic Sep 8, 2022
93bc768
Merge #103
bors[bot] Sep 8, 2022
061c0aa
SBI: introducing sbi compatibility
pgraubner Sep 15, 2022
7d5d587
SBI: upload static libs
pgraubner Sep 15, 2022
67b2fcd
SBI: fix formatting and CHANGELOG
pgraubner Sep 16, 2022
3e4c04f
SMODE: rename feature sbi to s-mode
pgraubner Sep 16, 2022
20837cf
SMODE: upload static libs
pgraubner Sep 16, 2022
68e99b3
SMODE: remove redundand paths
pgraubner Sep 19, 2022
e53deef
Merge #104
bors[bot] Sep 19, 2022
edf0387
release v0.10.0
almindor Nov 5, 2022
6644fa5
Merge #105
bors[bot] Nov 5, 2022
d66bf9f
update to riscv 0.10
tfx2001 Dec 24, 2022
3859409
Merge #108
bors[bot] Dec 26, 2022
bb86d34
release v0.10.1 with riscv CS fix
almindor Jan 18, 2023
fcc69ab
use v0.11.0 due to major dependency bump
almindor Jan 18, 2023
e48c03e
Merge #109
bors[bot] Jan 18, 2023
527ed05
fix: avoid rust-analyzer snake case warning
sethp Jan 21, 2023
1091528
Merge #110
bors[bot] Jan 22, 2023
a479977
moving to ghmq
romancardenas Jul 4, 2023
86d70ab
ready to merge
romancardenas Jul 4, 2023
5437af7
Merge pull request #115 from rust-embedded/ghmq
almindor Jul 4, 2023
0abe2ab
use core::arch::global_asm
romancardenas Jul 6, 2023
19c30c6
add .vscode to .gitignore
romancardenas Jul 6, 2023
70ec45e
Merge branch 'master' into global_asm
romancardenas Jul 6, 2023
11049a4
modify build CI task
romancardenas Jul 6, 2023
a949316
testing oor branch
onsdagens Jul 6, 2023
f823dd9
fix oor branch via linking
onsdagens Jul 6, 2023
47082d0
run workflow on new branch
onsdagens Jul 6, 2023
3358321
fix oor branch via linking
onsdagens Jul 6, 2023
213bc80
Merge branch 'global_asm_link' of github.com:onsdagens/riscv-rt into …
onsdagens Jul 6, 2023
8a54bb1
Merge pull request #116 from onsdagens/global_asm
romancardenas Jul 6, 2023
f182901
does this even matter
onsdagens Jul 6, 2023
3fa3c37
fix oor branch via linking
onsdagens Jul 6, 2023
fc48c00
fix oor branch via linking
onsdagens Jul 6, 2023
c861d19
Merge pull request #117 from onsdagens/global_asm_link
romancardenas Jul 7, 2023
9e589b5
Ready for PR
romancardenas Jul 8, 2023
15939f4
Merge pull request #118 from rust-embedded/global_asm
almindor Jul 22, 2023
e540f1e
Add feature single-hart
ivq Jul 30, 2023
c4f05d2
Merge pull request #119 from ivq/single_hart
almindor Aug 8, 2023
89be0f4
cargo clippy --fix
romancardenas Aug 11, 2023
a47aca1
Added clippy workflow
romancardenas Aug 11, 2023
db136b8
Merge pull request #120 from rust-embedded/clippy
almindor Aug 11, 2023
eef90a0
Implement r0 crate in assembly
coastalwhite Sep 22, 2023
1f29bd3
Impr: r0 loops to minimize instructions
coastalwhite Sep 28, 2023
6c517f2
Impr: add rv64 version of r0 assembly
coastalwhite Sep 29, 2023
01711b7
Doc: Adjust CHANGELOG.md
coastalwhite Sep 29, 2023
5612518
Fix: Add separate linkerscripts for rv32 and rv64
coastalwhite Oct 2, 2023
da226b6
Merge pull request #123 from coastalwhite/r0-in-asm
romancardenas Oct 2, 2023
16d0a81
Added GH Action to check CHANGELOG.md
romancardenas Oct 3, 2023
b3d0c9c
ready for PR
romancardenas Oct 3, 2023
6b1a4d2
trying to fix it
romancardenas Oct 3, 2023
8c2058e
add skip changelog label
romancardenas Oct 3, 2023
d9fb8e5
Added workflow to check invalid labels
romancardenas Oct 3, 2023
6d05bb6
minor changes
romancardenas Oct 3, 2023
26e2095
Update and rename gh_labels.yaml to label.yaml
romancardenas Oct 3, 2023
cc4f035
Merge pull request #124 from rust-embedded/check-changelog
romancardenas Oct 3, 2023
2338794
Remove label-check from merge_group
romancardenas Oct 3, 2023
ea1deea
Merge pull request #125 from rust-embedded/label-patch
MabezDev Oct 3, 2023
b84edd6
build.rs now adapts link.x for the target arch
romancardenas Nov 8, 2023
0631b3a
Ignore hartid in single-hart mode.
kevin-vigor Nov 2, 2023
448eec9
Merge pull request #126 from kevin-vigor/master
romancardenas Nov 9, 2023
1a22ec5
Fix setting incorrect sp if single-hart
ivq Nov 10, 2023
17185e9
Add 'single-hart' changelog entry
ivq Nov 10, 2023
408acae
Update doc on single-hart
ivq Nov 10, 2023
34e07c6
Merge pull request #128 from ivq/fix_single_hart_stack
romancardenas Nov 10, 2023
b737208
Ensure sp is 16-byte aligned
ivq Nov 10, 2023
0383469
Merge pull request #129 from ivq/sp_align
romancardenas Nov 13, 2023
f2b1dea
Merge branch 'master' into new_build
romancardenas Nov 16, 2023
721f107
Merge pull request #127 from rust-embedded/new_build
MabezDev Nov 16, 2023
0bae216
Merge remote-tracking branch 'riscv-rt/master' into add-riscv-rt
romancardenas Nov 17, 2023
cd474dd
Setting CI (WIP)
romancardenas Nov 17, 2023
612d58d
fix build.yaml
romancardenas Nov 17, 2023
edf4dac
separation of CI
romancardenas Nov 17, 2023
3d39bbf
changelog
romancardenas Nov 18, 2023
d7b4ae9
update Cargo.toml
romancardenas Nov 20, 2023
5407f38
Addressing review
romancardenas Nov 27, 2023
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10 changes: 10 additions & 0 deletions .github/workflows/changelog.yaml
Original file line number Diff line number Diff line change
Expand Up @@ -19,6 +19,8 @@ jobs:
filters: |
riscv:
- 'riscv/**'
riscv-rt:
- 'riscv-rt/**'

- name: Check for CHANGELOG.md (riscv)
if: steps.changes.outputs.riscv == 'true'
Expand All @@ -27,3 +29,11 @@ jobs:
changeLogPath: ./riscv/CHANGELOG.md
skipLabels: 'skip changelog'
missingUpdateErrorMessage: 'Please add a changelog entry in the riscv/CHANGELOG.md file.'

- name: Check for CHANGELOG.md (riscv-rt)
if: steps.changes.outputs.riscv-rt == 'true'
uses: dangoslen/changelog-enforcer@v3
with:
changeLogPath: ./riscv-rt/CHANGELOG.md
skipLabels: 'skip changelog'
missingUpdateErrorMessage: 'Please add a changelog entry in the riscv-rt/CHANGELOG.md file.'
32 changes: 25 additions & 7 deletions .github/workflows/clippy.yaml
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
on:
push:
branches: [ staging, trying, master ]
branches: [ master ]
pull_request:
merge_group:

Expand All @@ -14,28 +14,46 @@ jobs:
strategy:
matrix:
toolchain: [ stable, nightly ]
cargo_flags:
- "--no-default-features"
- "--all-features"
include:
# Nightly is only for reference and allowed to fail
- toolchain: nightly
experimental: true
runs-on: ubuntu-latest
continue-on-error: ${{ matrix.experimental || false }}
steps:
- uses: actions/checkout@v3
- uses: actions/checkout@v4
- uses: dtolnay/rust-toolchain@master
with:
toolchain: ${{ matrix.toolchain }}
components: clippy
- name: Run clippy
run: cargo clippy --all ${{ matrix.cargo_flags }} -- -D warnings
- name: Run clippy (no features)
run: cargo clippy --all --no-default-features -- -D warnings
- name: Run clippy (all features)
run: cargo clippy --all --all-features -- -D warnings

# Additonal clippy checks for riscv-rt
clippy-riscv-rt:
strategy:
matrix:
toolchain: [ stable, nightly ]
runs-on: ubuntu-latest
continue-on-error: ${{ matrix.experimental || false }}
steps:
- uses: actions/checkout@v4
- uses: dtolnay/rust-toolchain@master
with:
toolchain: ${{ matrix.toolchain }}
components: clippy
- name: Run clippy (s-mode)
run: cargo clippy --package riscv-rt --all --features=s-mode -- -D warnings
- name: Run clippy (single-hart)
run: cargo clippy --package riscv-rt --all --features=single-hart -- -D warnings

# Job to check that all the lint checks succeeded
clippy-check:
needs:
- clippy
- clippy-riscv-rt
runs-on: ubuntu-latest
if: always()
steps:
Expand Down
17 changes: 17 additions & 0 deletions .github/workflows/label.yaml
Original file line number Diff line number Diff line change
@@ -0,0 +1,17 @@
name: Check Labels

on:
pull_request:
types: [opened, synchronize, reopened, ready_for_review, labeled, unlabeled]

jobs:
label-check:
runs-on: ubuntu-latest
steps:
- uses: mheap/github-action-required-labels@v5
with:
mode: exactly
count: 0
labels: "work in progress, do not merge"
add_comment: true
message: "This PR is being prevented from merging because it presents one of the blocking labels: {{ provided }}."
52 changes: 52 additions & 0 deletions .github/workflows/riscv-rt.yaml
Original file line number Diff line number Diff line change
@@ -0,0 +1,52 @@
on:
push:
branches: [ master ]
pull_request:
merge_group:

name: Build check (riscv-rt)

jobs:
build:
strategy:
matrix:
# All generated code should be running on stable now, MRSV is 1.59.0
toolchain: [ stable, nightly, 1.59.0 ]
target:
- riscv32i-unknown-none-elf
- riscv32imc-unknown-none-elf
- riscv32imac-unknown-none-elf
- riscv64imac-unknown-none-elf
- riscv64gc-unknown-none-elf
example:
- empty
- multi_core
include:
# Nightly is only for reference and allowed to fail
- toolchain: nightly
experimental: true
runs-on: ubuntu-latest
continue-on-error: ${{ matrix.experimental || false }}
steps:
- uses: actions/checkout@v4
- uses: dtolnay/rust-toolchain@master
with:
toolchain: ${{ matrix.toolchain }}
targets: ${{ matrix.target }}
- name: Build (no features)
run: RUSTFLAGS="-C link-arg=-Triscv-rt/examples/device.x" cargo build --package riscv-rt --target ${{ matrix.target }} --example ${{ matrix.example }}
- name : Build example (s-mode)
run: RUSTFLAGS="-C link-arg=-Triscv-rt/examples/device.x" cargo build --package riscv-rt --target ${{ matrix.target }} --example ${{ matrix.example }} --features=s-mode
- name : Build example (single-hart)
run: RUSTFLAGS="-C link-arg=-Triscv-rt/examples/device.x" cargo build --package riscv-rt --target ${{ matrix.target }} --example ${{ matrix.example }} --features=single-hart
- name: Build example (all features)
run: RUSTFLAGS="-C link-arg=-Triscv-rt/examples/device.x" cargo build --package riscv-rt --target ${{ matrix.target }} --example ${{ matrix.example }} --all-features

# Job to check that all the builds succeeded
build-check:
needs:
- build
runs-on: ubuntu-latest
if: always()
steps:
- run: jq --exit-status 'all(.result == "success")' <<< '${{ toJson(needs) }}'
25 changes: 12 additions & 13 deletions .github/workflows/build.yaml → .github/workflows/riscv.yaml
Original file line number Diff line number Diff line change
@@ -1,10 +1,10 @@
on:
push:
branches: [ staging, trying, master ]
branches: [ master ]
pull_request:
merge_group:

name: Build check
name: Build check (riscv)

jobs:
# We check that the crate builds and links for all the toolchains and targets.
Expand All @@ -19,37 +19,36 @@ jobs:
- riscv32imac-unknown-none-elf
- riscv64imac-unknown-none-elf
- riscv64gc-unknown-none-elf
cargo_flags: [ "--no-default-features", "--all-features" ]
include:
# Nightly is only for reference and allowed to fail
- toolchain: nightly
experimental: true
runs-on: ubuntu-latest
continue-on-error: ${{ matrix.experimental || false }}
steps:
- uses: actions/checkout@v3
- uses: actions/checkout@v4
- uses: dtolnay/rust-toolchain@master
with:
toolchain: ${{ matrix.toolchain }}
targets: ${{ matrix.target }}
- name: Build library
run: cargo build --target ${{ matrix.target }} ${{ matrix.cargo_flags }}
- name: Build (no features)
run: cargo build --package riscv --target ${{ matrix.target }}
- name: Build (all features)
run: cargo build --package riscv --target ${{ matrix.target }} --all-features

# On MacOS, Ubuntu, and Windows, we at least make sure that the crate builds and links.
build-others:
strategy:
matrix:
os:
- macos-latest
- ubuntu-latest
- windows-latest
cargo_flags: [ "--no-default-features", "--all-features" ]
os: [ macos-latest, ubuntu-latest, windows-latest ]
runs-on: ${{ matrix.os }}
steps:
- uses: actions/checkout@v3
- uses: dtolnay/rust-toolchain@stable
- name: Build crate for host OS
run: cargo build ${{ matrix.cargo_flags }}
- name: Build (no features)
run: cargo build --package riscv
- name: Build (all features)
run: cargo build --package riscv --all-features

# Job to check that all the builds succeeded
build-check:
Expand Down
4 changes: 2 additions & 2 deletions .github/workflows/rustfmt.yaml
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
on:
push:
branches: [ staging, trying, master ]
branches: [ master ]
pull_request:
merge_group:

Expand All @@ -10,7 +10,7 @@ jobs:
rustfmt:
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v3
- uses: actions/checkout@v4
- uses: dtolnay/rust-toolchain@stable
with:
components: rustfmt
Expand Down
1 change: 1 addition & 0 deletions Cargo.toml
Original file line number Diff line number Diff line change
Expand Up @@ -2,4 +2,5 @@
resolver = "2"
members = [
"riscv",
"riscv-rt",
]
39 changes: 12 additions & 27 deletions README.md
Original file line number Diff line number Diff line change
@@ -1,41 +1,26 @@
[![crates.io](https://img.shields.io/crates/d/riscv.svg)](https://crates.io/crates/riscv)
[![crates.io](https://img.shields.io/crates/v/riscv.svg)](https://crates.io/crates/riscv)
[![Build Status](https://travis-ci.org/rust-embedded/riscv.svg?branch=master)](https://travis-ci.org/rust-embedded/riscv)
# RISC-V crates

# `riscv`
This repository contains various crates useful for writing Rust programs on RISC-V microcontrollers:

> Low level access to RISC-V processors
* [`riscv`]: CPU peripheral access and intrinsics
* [`riscv-rt`]: Startup code and interrupt handling

This project is developed and maintained by the [RISC-V team][team].

## [Documentation](https://docs.rs/crate/riscv)

## Minimum Supported Rust Version (MSRV)

This crate is guaranteed to compile on stable Rust 1.60 and up. It *might*
compile with older versions but that may change in any new patch release.

## License

Copyright 2019-2022 [RISC-V team][team]
This project is developed and maintained by the [RISC-V team][team].

Permission to use, copy, modify, and/or distribute this software for any purpose
with or without fee is hereby granted, provided that the above copyright notice
and this permission notice appear in all copies.
### Contribution

THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH
REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND
FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT,
INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS
OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF
THIS SOFTWARE.
Unless you explicitly state otherwise, any contribution intentionally submitted for inclusion in the
work by you, as defined in the Apache-2.0 license, shall be dual licensed as above, without any
additional terms or conditions.

## Code of Conduct

Contribution to this crate is organized under the terms of the [Rust Code of
Conduct][CoC], the maintainer of this crate, the [RISC-V team][team], promises
to intervene to uphold that code of conduct.

[CoC]: CODE_OF_CONDUCT.md
[`riscv`]: https://crates.io/crates/riscv
[`riscv-rt`]: https://crates.io/crates/riscv-rt
[team]: https://github.com/rust-embedded/wg#the-risc-v-team
[CoC]: CODE_OF_CONDUCT.md
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