Patch Release

Pull Requests

1. #203 - Updates to Clink python to support latest rogue
2. #201 - Ltc2270 Python Register Mapping Bug Fix
3. #202 - Python bug fix for AxiMicronP30.py

Pull Request Details

Updates to Clink python to support latest rogue

Author:	Ryan Herbst [email protected]
Date:	Tue Apr 3 22:14:00 2018 -0700
Pull:	#203 (16 additions, 16 deletions, 2 files changed)
Branch:	slaclab/clink_deprecate

Notes:

Remove deprecated class method decorators for serial send commands.

Fix reqFrame call for new API in serial send commands.

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Ltc2270 Python Register Mapping Bug Fix

Author:	Larry Ruckman [email protected]
Date:	Tue Apr 3 22:14:49 2018 -0700
Pull:	#201 (11 additions, 11 deletions, 1 files changed)
Branch:	slaclab/Ltc2270-python-fix

Notes:

Description

Fixed the register mapping. I didn't know about this until rogue v2.7.0, which outputs all overlapping registers.

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Python bug fix for AxiMicronP30.py

Author:	Larry Ruckman [email protected]
Date:	Tue Apr 3 22:15:11 2018 -0700
Pull:	#202 (1 additions, 1 deletions, 1 files changed)
Branch:	slaclab/AxiMicronP30

Notes:

Description

Not enough "size" allocated for _rawWrite/_rawRead. Fixed it in d61db37 commit.

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Release v1.7.3

Overview

This is a patch release with a few critical bug fixes and some small enhancements as described in the Pull Request list below.

Pull Requests

1. #196 - Added several new pyrogue Devices and enhanced some existing ones
2. #199 - Fixed RSSI TX FSM bug
3. #195 - Updates to UDP pyrogue Devices
4. #192 - Better display of IP address and port numbers
5. #197 - RSSI FlowControl Bug Fix

Pull Request Details

Added several new pyrogue Devices and enhanced some existing ones

Author:	Larry Ruckman [email protected]
Date:	Tue Mar 27 14:56:39 2018 -0700
Pull:	#196 (1323 additions, 336 deletions, 14 files changed)
Branch:	slaclab/overlap_var-llr

Notes:

Description

1. Updates for rogue v2.7.0
2. Added SA56004ATK, LTC2945, and TCN75AVOA713 device classes
3. Updated _AxiSysMonUltraScale.py to outputs simliar to XADC
4. Updated the RSSI bandwidth/rate variable names

JIRA

ESCORE-330
ESCRYODET-94

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Fixed RSSI TX FSM bug

Author:	Larry Ruckman [email protected]
Date:	Mon Apr 2 10:15:57 2018 -0700
Pull:	#199 (209 additions, 109 deletions, 5 files changed)
Branch:	slaclab/rssi-dev

Notes:

Description

1. RSSI TX FSM flow control bug fix (1fcfb71)
2. V1 Packeterizer code clean up (08a98be/5111f10)
3. Added auto polling to _SsiPrbsRx.py and _SsiPrbsTx.py (d398dd5)

I have regression tested this on the dev-board-example target for this corner case for both _rawWrite() and PRBS TX/RX streams.

JIRA

ESCORE-339

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Updates to UDP pyrogue Devices

Author:	Larry Ruckman [email protected]
Date:	Wed Mar 21 17:19:10 2018 -0700
Pull:	#195 (42 additions, 37 deletions, 3 files changed)
Branch:	slaclab/udp-link-var

Notes:

1. Updating any python with size if rawWrite/rawRead used
2. Updating the UDP LinkVariables

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Better display of IP address and port numbers

Author:	Larry Ruckman [email protected]
Date:	Fri Mar 16 15:27:44 2018 -0700
Pull:	#192 (55 additions, 0 deletions, 2 files changed)
Branch:	slaclab/ESCORE-332
Jira:	https://jira.slac.stanford.edu/issues/ESCORE-332

Notes:

Added LinkVariable to make the UDP IP address and Port number human readable

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RSSI FlowControl Bug Fix

Author:	Larry Ruckman [email protected]
Date:	Wed Mar 28 13:54:12 2018 -0700
Pull:	#197 (2 additions, 1 deletions, 1 files changed)
Branch:	slaclab/rssi-dev

Notes:

Description

We previously had this:

constant FIFO_PAUSE_THRESH_C : positive := ((2**FIFO_ADDR_WIDTH_C)-1) - 16;  -- FIFO_FULL - padding (128 bytes)

SEGMENT_ADDR_SIZE_G = 7, which is 2^7 = 128 words
128 words (1024B) > 16 padding
In this pull request, we change the threshold to this:

constant FIFO_PAUSE_THRESH_C : positive := (2**FIFO_ADDR_WIDTH_C) - (2**(SEGMENT_ADDR_SIZE_G+1));  -- pause threshold = FIFO_FULL - (2 x segment buffers)

This makes sure there's 2 times more buffer room in the FIFO before bursting from the BRAM to the FIFO when SEGMENT_ADDR_SIZE_G > 6, FIFO_PAUSE_THRESH_C becomes effectively (2**FIFO_ADDR_WIDTH_C)/2.
I have confirmed in dev-board-example that this works.
slaclab/dev-board-examples@e61df85

JIRA

ESROGUE-202 (related)

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SURF v1.7.2

Pull Requests

1. #191 - Remove bit_vector use in Crc32Rtl

Pull Request Details

Remove bit_vector use in Crc32Rtl

Author:	Benjamin Reese [email protected]
Date:	Thu Mar 15 11:58:50 2018 -0700
Pull:	#191 (19 additions, 17 deletions, 1 files changed)
Branch:	slaclab/ben-crc-fix

Notes:

The CRC_INIT generic was a bit_vector. There was an improper conversion call that caused synthesis to fail. As part of this fix, all bit_vector use as been removed.

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SURF v1.7.1

Pull Requests

1. #190 - Add back GthUltrascaleQuadPll EN_DRP_G generic

Pull Request Details

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Add back GthUltrascaleQuadPll EN_DRP_G generic

Author:	Benjamin Reese [email protected]
Date:	Wed Mar 14 16:01:17 2018 -0700
Pull:	#190 (3 additions, 2 deletions, 1 files changed)
Branch:	slaclab/en-drp

Notes:

This generic somehow got erroneously removed in #147.

SURF v1.7.0

Pull Requests

1. #178 - ESROGUE-153 - AxiStreamPacketizerV2 enhancements
2. #147 - Remove AXI_ERROR_RESP_G
3. #188 - Pyrogue Device fixes for Ad5780 and Ltc2270
4. #186 - ESLCOMMON-205 - Set proper header on Pgp3 opcode transmission

Pull Request Details

ESROGUE-153 - AxiStreamPacketizerV2 enhancements

Author:	Benjamin Reese [email protected]
Date:	Tue Mar 13 17:04:04 2018 -0700
Pull:	#178 (834 additions, 471 deletions, 12 files changed)
Branch:	slaclab/ESROGUE-153
Jira:	https://jira.slac.stanford.edu/issues/ESROGUE-153

Notes:

Lots of changes to AxiStreamPacketizerV2 and modules that use it

AxiStreamPacketizerV2/AxiStreamDepacketizerV2

• Fixed some TKEEP bugs in the Packetizer
• Packetizer/Depacketizer now have generics to optionally include the header and tail in the CRC calculation.
• The Packetizer protocol has changed so that the CRC is cumulative over every packet of a frame.

RSSI

• Enable CRC by default when interleaving

PGP3

• The change to cumulative CRC is carried into the PGP3 protocol
• This means that PGP3 instances built previously will not be compatible with this!

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Remove AXI_ERROR_RESP_G

Author:	Benjamin Reese [email protected]
Date:	Wed Mar 14 09:28:50 2018 -0700
Pull:	#147 (368 additions, 801 deletions, 152 files changed)
Branch:	slaclab/rem-axi-err-resp

Notes:

I've gone through every module in SURF and removed the AXI_ERROR_RESP_G generic.

AxiLiteCrossbar and AxiLiteAsync still have it. If you need to mask AXI errors, you should do it at the top-most crossbar or synchronizer, where you connect to the bus that cannot tolerate errors.

AxiLiteEmpty also still has it, as you may want a particular instance to respond with OK to every access.

I also left it in AxiStreamDmaV2, because the generic is passed down to a crossbar which may be the top level. If this is not the case then we should remove it here too

This will obviously break some builds, but the fix is pretty easy. Just remove the generic association from the instantiation.

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Pyrogue Device fixes for Ad5780 and Ltc2270

Author:	Larry Ruckman [email protected]
Date:	Wed Mar 14 09:57:55 2018 -0700
Pull:	#188 (8 additions, 4 deletions, 2 files changed)
Branch:	slaclab/lcls2-prl-dev

Notes:

Ad5780 - Fixed Variable/method name conflict
Ltc2779 - Properly name array Variables

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ESLCOMMON-205 - Set proper header on Pgp3 opcode transmission

Author:	Benjamin Reese [email protected]
Date:	Mon Mar 12 12:18:51 2018 -0700
Pull:	#186 (1 additions, 0 deletions, 1 files changed)
Branch:	slaclab/ESLCOMMON-205
Jira:	https://jira.slac.stanford.edu/issues/ESLCOMMON-205

Notes:

The header field wasn't being set to PGP3_K_HEADER_C ("10") when sending OpCodes. This has been fixed.

https://jira.slac.stanford.edu/browse/ESLCOMMON-205

v1.3.0

Stable version after reorganization.

v1.2.12

Stable version before python file re-org

v1.1.1

Minor changes to V1 AXI DMA.
Added V2 AXI DMA.

Minor Release v1.1.0

Pull Requests Since v1.0.1

Unlabeled

1. #12 - Merging master changes into ESCORE-167 branch
2. #10 - adding PhyReady WDT to 1GbE cores
3. #11 - Merge Esrcecore 24 fixes

Pull Request Details

adding PhyReady WDT to 1GbE cores

Author:	Larry Ruckman [email protected]
Date:	Wed May 20 16:36:30 2020 -0700
Pull:	#10 (80 additions, 80 deletions, 5 files changed)
Branch:	slaclab/ESCORE-551
Jira:	https://jira.slac.stanford.edu/issues/ESCORE-551

Notes:

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Merge Esrcecore 24 fixes

Author:	Ryan Herbst [email protected]
Date:	Mon Dec 7 14:13:35 2020 -0800
Pull:	#11 (22 additions, 13 deletions, 1 files changed)
Branch:	slaclab/gh-actions

Notes:

Update to AxiStreamDmaWrite cache buffer to fixed tkeep corruption.

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Merging master changes into ESCORE-167 branch

Author:	Ryan Herbst [email protected]
Date:	Mon Dec 7 14:27:09 2020 -0800
Pull:	#12 (140 additions, 109 deletions, 11 files changed)
Branch:	slaclab/gh-actions

Notes:

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