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Patch Release

12 Apr 17:22
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v1.9.9
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Patch Release

Pull Requests

  1. #406 - v1.9.9 release candidate
  2. #405 - Clink Development Updates
  3. #412 - adding Sgmii88E1111LvdsUltraScale module
  4. #396 - Rogue Tcp features
  5. #415 - AxiStreamDmaV2: DMA Write Ordering
  6. #411 - EPIX HR Development Updates
  7. #407 - AXI-Lite wrapper for AxiStreamBatcher
  8. #408 - Pyrogue Device for AxiStreamScatterGather
  9. #409 - Optionally cache SPI memory in AxiSpiMaster
  10. #417 - Rogue Device bugfixes
  11. #410 - Update AxiDualPortRam.vhd
  12. #416 - UartAxiLite bug fix
  13. #414 - Change counter from integer to SLV so it can be set via AXI-Lite
  14. #413 - Updating ruckus submodule lock due to RogueTcpRogueTcp dependence

Pull Request Details

v1.9.9 release candidate
Author: Larry Ruckman [email protected]
Date: Fri Apr 12 10:12:22 2019 -0700
Pull: #406 (6182 additions, 1847 deletions, 91 files changed)
Branch: slaclab/pre-release

Notes:

Description

  • Rogue Tcp features (#396)
  • Clink Development Updates (#405)
  • AXI-Lite wrapper for AxiStreamBatcher (#407)
  • Optionally cache SPI memory in AxiSpiMaster (#409)
  • Update AxiDualPortRam.vhd (#410)
  • Pyrogue Device for AxiStreamScatterGather (#408)
  • UartAxiLite bug fix (#416)
  • AxiStreamDmaV2: DMA Write Ordering (#415)
  • Clink Development Updates (#405)
  • Rogue Device bugfixes (#417)

Clink Development Updates
Author: Larry Ruckman [email protected]
Date: Fri Apr 12 09:55:28 2019 -0700
Pull: #405 (4378 additions, 1049 deletions, 38 files changed)
Branch: slaclab/clink-dev

Notes:

Description

  • adding bypass reg to AxiStreamBatcherEventBuilder
  • adding _UartPiranha4.py
  • removing all the in UartOpal000.py since already include in ClinkSerialTx at line42
  • adding Lmk61e2.py & Pca9535.py
  • Si5345.py for rawWrite() overlap exceptions

adding Sgmii88E1111LvdsUltraScale module
Author: Larry Ruckman [email protected]
Date: Wed Apr 10 10:39:46 2019 -0700
Pull: #412 (845 additions, 485 deletions, 19 files changed)
Branch: slaclab/Sgmii88E1111LvdsUltraScale

Notes:

Description

  • adding Sgmii88E1111LvdsUltraScale module
  • Code based on Till's work in slaclab/dev-board-examples/firmware/targets/XilinxKCU105DevBoard/Kcu105GigE

Rogue Tcp features
Author: Larry Ruckman [email protected]
Date: Thu Mar 21 17:01:09 2019 -0700
Pull: #396 (470 additions, 239 deletions, 18 files changed)
Branch: slaclab/tcp-features

Notes:

Description

  • Add RoguePgp2bSim to wrap Pgp2b around RogueTcpStream.
  • Set TCP port range for Rogue sim modules.
  • Make RogueSideBand bi-directional
  • Update default sim version of GTP to 2.0
  • Fix bug in RogueTcpStream.c where TUserFirst got dropped on single txn frames.

AxiStreamDmaV2: DMA Write Ordering
Author: Larry Ruckman [email protected]
Date: Fri Apr 12 09:55:03 2019 -0700
Pull: #415 (303 additions, 317 deletions, 4 files changed)
Branch: slaclab/dma_ordering

Notes:

Description

  • Adding a special mux for enforcing the write descriptor is received by the software after the data
  • Changed all the AXI Stream Interface arrays to end in "s" (coding standard)
  • Changed all the AXI4 Memory Interface arrays to end in "s" (coding standard)
  • Removed pause support to the descriptor module

EPIX HR Development Updates
Author: Larry Ruckman [email protected]
Date: Tue Apr 2 13:40:31 2019 -0700
Pull: #411 (159 additions, 52 deletions, 7 files changed)
Branch: slaclab/epix-dev

Notes:

Description

  • Many changes including critical bug fix of AD9249 for ultrascale family.

AXI-Lite wrapper for AxiStreamBatcher
Author: Benjamin Reese [email protected]
Date: Wed Mar 27 08:27:59 2019 -0700
Pull: #407 (190 additions, 4 deletions, 4 files changed)
Branch: slaclab/batcher-axil

Notes:

Description

  • Added an AXI-Lite wrapper for setting the 3 AxiStreamBatcher parameters.
  • Added pyrogue Device for AxiStreamBatcherAxil
  • Extended maxClkGap to 32 bits.

Pyrogue Device for AxiStreamScatterGather
Author: Benjamin Reese [email protected]
Date: Fri Mar 29 09:47:05 2019 -0700
Pull: #408 (86 additions, 0 deletions, 2 files changed)
Branch: slaclab/python-scatter-gather

Notes:

Description

Added a pyrogue Device for the AxiStreamScatterGather module.
This is useful for debugging.

Optionally cache SPI memory in AxiSpiMaster
Author: Larry Ruckman [email protected]
Date: Wed Mar 27 14:38:05 2019 -0700
Pull: #409 (42 additions, 6 deletions, 1 files changed)
Branch: slaclab/shadow-spi

Notes:

Add SHADOW_EN_G to AxiSpiMaster. If enabled will generate a single port RAM to shadow the SPI device memory
- writes go to SPI and shadow memory
- reads return shadow memory

Description

Details

JIRA

Related

Rogue Device bugfixes
Author: Larry Ruckman [email protected]
Date: Fri Apr 12 10:03:19 2019 -0700
Pull: #417 (7 additions, 9 deletions, 3 files changed)
Branch: slaclab/hps-dev

Notes:

Description

This PR fixes a few incorrect Rogue Variable definitions.

Update AxiDualPortRam.vhd
Author: Larry Ruckman [email protected]
Date: Wed Mar 27 14:38:23 2019 -0700
Pull: #410 (5 additions, 5 deletions, 1 files changed)
Branch: slaclab/AxiDualPortRam-reset

Notes:

Description

  • Tying user reset on RAMs to 0x0 (help with performance)

UartAxiLite bug fix
Author: Benjamin Reese [email protected]
Date: Fri Apr 12 09:49:38 2019 -0700
Pull: #416 (3 additions, 1 deletions, 1 files changed)
Branch: slaclab/uart-fix

Notes:

Description

Fix UartAxiLite to properly reset address and data between transactions.

Change counter from integer to SLV so it can be set via AXI-Lite
Author: Larry Ruckman [email protected]
Date: Fri Apr 5 13:27:27 2019 -0700
Pull: #414 (2 additions, 2 deletions, 1 files changed)
Branch: slaclab/ESCORE-416
Jira: https://jira.slac.stanford.edu/issues/ESCORE-416

Notes:

Description

A counter was declared as a natural. This caused synthesis to fail when passed to axiSlaveRegister().

Updating ruckus submodule lock due to RogueTcpRogueTcp dependence
Author: Larry Ruckman [email protected]
Date: Wed Apr 3 07:59:59 2019 -0700
Pull: #413 (1 additions, 1 deletions, 1 files changed)
Branch: slaclab/RogueTcp-ruckus-dependence

Notes:

Description

  • Updating ruckus submodule lock due to RogueTcpRogueTcp dependence
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Patch Release

20 Mar 05:35
@ruck314 ruck314
v1.9.8
8c50179
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Patch Release

Pull Requests

  1. #400 - v1.9.8 release candidate
  2. #350 - RSSI Version 1b Release
  3. #382 - Misc. Ethernet Updates
  4. #399 - Clink Development Updates
  5. #385 - AxiDualPortRam & RSSI Update
  6. #402 - More CLink Development Updates
  7. #393 - Updates from CamerLink-Gateway development
  8. #401 - Update XPM wrappers to allow up to 100 READ_LATENCY_G.
  9. #388 - Fix hardReset, softReset and countReset for PGPv2b
  10. #394 - Fix AXI Lite protocol bug in RogueTcpMemory
  11. #403 - Latch integrator output valid
  12. #397 - adding ACK/NAK response detection to ClinkSerialRx.py
  13. #398 - Fix for ADC32RF45 pyrogue
  14. #392 - Enable synchronizer on status bits for TenGigEth Axil registers.
  15. #389 - protocols/pgp/pgp2b/gtp7: Remove partial open port assignments

Pull Request Details

v1.9.8 release candidate
Author: Larry Ruckman [email protected]
Date: Tue Mar 19 22:32:42 2019 -0700
Pull: #400 (5919 additions, 1510 deletions, 121 files changed)
Branch: slaclab/pre-release

Notes:

Description

  • protocols/pgp/pgp2b/gtp7: Remove partial open port assignments (#389)
  • Enable synchronizer on status bits for TenGigEth Axil registers. (#392)
  • Fix hardReset, softReset and countReset for PGPv2b (#388)
  • RSSI Version 1b Release (#350)
  • Updates from CamerLink-Gateway development (#393, #399, #402)
  • Misc. Ethernet Updates (#382)
  • Fix for ADC32RF45 pyrogue (#398)
  • AxiDualPortRam & RSSI Update (#385, #401)
  • Fix AXI Lite protocol bug in RogueTcpMemory (#394)
  • Latch integrator output valid (#403)

RSSI Version 1b Release
Author: Larry Ruckman [email protected]
Date: Fri Mar 8 11:44:09 2019 -0800
Pull: #350 (3385 additions, 17 deletions, 23 files changed)
Branch: slaclab/axi-rssi-dev

Notes:

Description

  • RSSI Version 1b has zero changes to the RSSI Version 1 "protocol" (recycling most of the existin RSSI firmware)
  • This version using an external AXI memory interface for buffering (instead of internal BRAMs)
  • This opens up the possibility to do large (up to 256 segment) buffering via external memory (like DDR)
  • RSSI + PackerV2 = 6.4kLUTs, 6.9kREG, 3 RAMB36, 3 DSP48

Misc. Ethernet Updates
Author: Larry Ruckman [email protected]
Date: Fri Mar 8 14:24:42 2019 -0800
Pull: #382 (558 additions, 768 deletions, 64 files changed)
Branch: slaclab/eth-dev

Notes:

Description

  • In EthMacTxExportXgmii.vhd: Optimized 'Layer 2 Ethernet frame' min size from 72 octets to 65 octets (64 octets is the limit with respect to IEEE 802.3)
  • Overhauled the EthMacTb.vhd to do a byte sweep from 16 octets to 260 octets to test for zero padding implementation and all byte level corner cases in the XGMII TX export and XGMII RX export
  • Overhauled the UdpEngineTb.vhd to sweep through different PRBS sizes
  • misc ruckus.tcl updates

Clink Development Updates
Author: Larry Ruckman [email protected]
Date: Thu Mar 14 16:01:53 2019 -0700
Pull: #399 (886 additions, 363 deletions, 14 files changed)
Branch: slaclab/ClinkSerialRx-update

Notes:

Description

  • adding rstPll and rstFsm commands
  • changing ClinkData.REG_INIT_C.delay to zero
  • execute ResetFsm() after YAML load automatically
  • adding Blowoff debugging register

AxiDualPortRam & RSSI Update
Author: Larry Ruckman [email protected]
Date: Tue Mar 12 15:43:04 2019 -0700
Pull: #385 (514 additions, 191 deletions, 13 files changed)
Branch: slaclab/AxiDualPortRam-update

Notes:

Description

  • Adding URAM support toAxiDualPortRam & RSSI for Ultrascale+

More CLink Development Updates
Author: Larry Ruckman [email protected]
Date: Mon Mar 18 10:17:49 2019 -0700
Pull: #402 (337 additions, 170 deletions, 7 files changed)
Branch: slaclab/ClinkSerialRx-update

Notes:

Description

  • adding soft/hard resets to AxiStreamBatcherEventBuilder.vhd
  • adding cntRst and lockCnt status counters
  • removed r.byteData.lv = 0x0 condition from dropFrame

Updates from CamerLink-Gateway development
Author: Larry Ruckman [email protected]
Date: Fri Mar 8 14:22:57 2019 -0800
Pull: #393 (230 additions, 22 deletions, 8 files changed)
Branch: slaclab/clink-dev

Notes:

Description

  • fixed memory overlap in AxiStreamMonitoring.py
  • updating AxiVersion.py print out (useful when you have more than 1 AxiVersion in your SW)
  • prevent CLink bandrate of zero
  • updating ClinkChannel.py
  • adding AxiStreamBatcherEventBuilder.py
  • bug fix for AxiStreamBatcherEventBuilder.vhd when r.timeout /= 0

Update XPM wrappers to allow up to 100 READ_LATENCY_G.
Author: Larry Ruckman [email protected]
Date: Mon Mar 18 10:20:10 2019 -0700
Pull: #401 (35 additions, 17 deletions, 5 files changed)
Branch: slaclab/xpm-mem-dev

Notes:

Description

Update XPM wrappers to allow up to 100 READ_LATENCY_G.
Update AxiDualPortRamp to allow up to READ_LATENCY = 3

Fix hardReset, softReset and countReset for PGPv2b
Author: Benjamin Reese [email protected]
Date: Fri Mar 8 11:37:37 2019 -0800
Pull: #388 (12 additions, 10 deletions, 1 files changed)
Branch: slaclab/pgp-rogue-fix

Notes:

Description

The Device was defining hardReset, softReset and countReset functions in the constructor. These need to be methods.

Fix AXI Lite protocol bug in RogueTcpMemory
Author: Benjamin Reese [email protected]
Date: Thu Mar 14 20:47:11 2019 -0700
Pull: #394 (10 additions, 8 deletions, 1 files changed)
Branch: slaclab/tcp-memory-fix

Notes:

Description

Fixed a bug in RogueTcpMemory.c that caused to it start the next transaction before the bus was ready.

Details

Master bus needs to wait for BVALID / RVALID to go low in response to BREADY / RREADY before starting the next transaction.

Note

I haven't verified that writes work yet.

Latch integrator output valid
Author: Larry Ruckman [email protected]
Date: Tue Mar 19 22:23:21 2019 -0700
Pull: #403 (11 additions, 6 deletions, 1 files changed)
Branch: slaclab/update_boxcar

Notes:

This allows the integrator to run in a mode where the putput valid is held until acked. The ack signal does not act as flow control.

adding ACK/NAK response detection to ClinkSerialRx.py
Author: Larry Ruckman [email protected]
Date: Mon Mar 11 21:57:15 2019 -0700
Pull: #397 (6 additions, 1 deletions, 1 files changed)
Branch: slaclab/ClinkSerialRx-update

Notes:

Description

  • adding ACK/NAK response detection to ClinkSerialRx.py

Fix for ADC32RF45 pyrogue
Author: Larry Ruckman [email protected]
Date: Tue Mar 12 15:27:37 2019 -0700
Pull: #398 (1 additions, 1 deletions, 1 files changed)
Branch: slaclab/cryo-pyrogue-fix

Notes:

Description

Fix pyrogue for Adc32Rf45

Enable synchronizer on status bits for TenGigEth Axil registers.
Author: Larry Ruckman [email protected]
Date: Wed Mar 6 15:39:50 2019 -0800
Pull: #392 (1 additions, 1 deletions, 1 files changed)
Branch: slaclab/tenGigEthRegSynchronizer

Notes:

Description

The TenGigEthReg module feature a synchronizer for status bits which are read
into AXIL registers. The module assumes that all status bits originate in the
same clock domain as the module itself and disables the synchronizer.

However, there are some bits which originate in a different clock domain. This
PR simply enables the (already coded) synchronizer.

Details

Some of the status bits:

gtTxRst,
gtRxRst,
rstCntDone,
rxRstdone,
txRstdone

are not generated in the target clock domain (phyClk).
Probably not that critical, but nevertheless...

(bits 17, 16, 12, 13, 14)

protocols/pgp/pgp2b/gtp7: Remove partial open port assignments
Author: Benjamin Reese [email protected]
Date: Wed Mar 6 09:15:50 2019 -0800
Pull: #389 (0 additions, 2 deletions, 2 files changed)
Branch: slaclab/hps-dev

Notes:

Description

Remove partial open port vector assignments.

Details

VHDL technically doesn't allow vector port assignments where one index is assigned to open. VCS complains about this. This PR removes to such assignments in pgp2b/gtp7.

There are a whole bunch of commits because this was a development branch ...

Read more
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Patch Release

05 Mar 21:22
@ruck314 ruck314
v1.9.7
aab96e9
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Patch Release

Pull Requests

  1. #387 - v1.9.7 release candidate
  2. #376 - Upgrading legacy rogue stream sim wrap
  3. #386 - Add generic boxcar integrator
  4. #380 - Convert simulation receivers to non blocking instead of timeout
  5. #375 - AxiStreamTap.vhd & AxiStreamBatcherEventBuilder.vhd Update
  6. #384 - python/surf/devices/micron/ & MmcmEmulation.vhd update
  7. #377 - AxiVersion.vhd Update
  8. #378 - Update AxiVersion with better use of LinkVariables
  9. #381 - adding StdMatch() fucntion to StdRtlPkg.vhd
  10. #379 - Allow dontcares in AxiLiteCrossbar config
  11. #374 - AxiStreamBatcher.vhd Update
  12. #383 - Remove std_ulogic_vector variant of StdMatch()

Pull Request Details

v1.9.7 release candidate
Author: Larry Ruckman [email protected]
Date: Tue Mar 5 13:21:11 2019 -0800
Pull: #387 (899 additions, 851 deletions, 29 files changed)
Branch: slaclab/pre-release

Notes:

Description

  • Allow dontcares in AxiLiteCrossbar config (#379)
  • Adding StdMatch() fucntion to StdRtlPkg.vhd (#381)
  • Convert simulation receivers to non blocking instead of timeout (#380)
  • Update AxiVersion with better use of LinkVariables (#378)
  • Upgrading legacy rogue stream sim wrap (#376)
  • AxiVersion.vhd Update (#377)
  • AxiStreamTap.vhd & AxiStreamBatcherEventBuilder.vhd Update (#375)
  • AxiStreamBatcher.vhd Update (#374)
  • python/surf/devices/micron/ & MmcmEmulation.vhd update (#384)
  • Add generic boxcar integrator (#386)

Upgrading legacy rogue stream sim wrap
Author: Larry Ruckman [email protected]
Date: Wed Feb 20 08:49:08 2019 -0800
Pull: #376 (127 additions, 384 deletions, 13 files changed)
Branch: slaclab/upgrading-legacy-RogueStreamSimWrap

Notes:

Description

  • adding 256 TDEST support to RogueTcpStreamWrap
  • removing unused sim source code
  • upgrading protocols/pgp/pgp3 to RogueTcpStreamWrap

Add generic boxcar integrator
Author: Larry Ruckman [email protected]
Date: Tue Mar 5 11:55:38 2019 -0800
Pull: #386 (382 additions, 105 deletions, 3 files changed)
Branch: slaclab/generic_integrator

Notes:

This is a generic boxcar integrator which can operate at the full clock rate and supports a configurable integration time.

This includes a test bench which tests changing boxcar sizes and different input valid spacings.

Convert simulation receivers to non blocking instead of timeout
Author: Larry Ruckman [email protected]
Date: Mon Feb 25 16:52:07 2019 -0800
Pull: #380 (84 additions, 112 deletions, 6 files changed)
Branch: slaclab/fix_blocking

Notes:

The previous versions were not doing non-blocking receive calls to the zeromq sockets. Instead they were waiting for a period of time. This was causing simulations to run slow.

AxiStreamTap.vhd & AxiStreamBatcherEventBuilder.vhd Update
Author: Larry Ruckman [email protected]
Date: Tue Feb 19 15:44:31 2019 -0800
Pull: #375 (118 additions, 49 deletions, 2 files changed)
Branch: slaclab/ruckman-dev

Notes:

Description

  • Exposing ILEAVE_ON_NOTVALID_G & ILEAVE_REARB_G in AxiStreamTap.vhd
  • Adding optional timeout feature to AxiStreamBatcherEventBuilder.vhd

python/surf/devices/micron/ & MmcmEmulation.vhd update
Author: Larry Ruckman [email protected]
Date: Tue Mar 5 12:07:55 2019 -0800
Pull: #384 (49 additions, 106 deletions, 4 files changed)
Branch: slaclab/memory-overlap-bug-fix

Notes:

Description

  • Resolved the memory overlaps in python/surf/devices/micron/
  • MmcmEmulation.vhd update

AxiVersion.vhd Update
Author: Larry Ruckman [email protected]
Date: Wed Feb 20 08:37:48 2019 -0800
Pull: #377 (74 additions, 67 deletions, 2 files changed)
Branch: slaclab/AxiVersion-update

Notes:

Description

  • Changing AUTO_RELOAD_TIME_G from real to positive
  • Require for CLK of 250 MHz and 10 sec reload time without going out-of-range of integer (2147483647)

Update AxiVersion with better use of LinkVariables
Author: Benjamin Reese [email protected]
Date: Mon Feb 25 11:31:41 2019 -0800
Pull: #378 (31 additions, 28 deletions, 1 files changed)
Branch: slaclab/ESROGUE-297
Jira: https://jira.slac.stanford.edu/issues/ESROGUE-297

Notes:

This update takes advantage of LinkVariables to parse the buildstring. A hardware read will only be called when the get() method is called on one of the link variables. I also updated the upTime link variable.

adding StdMatch() fucntion to StdRtlPkg.vhd
Author: Larry Ruckman [email protected]
Date: Tue Feb 26 09:22:50 2019 -0800
Pull: #381 (33 additions, 0 deletions, 1 files changed)
Branch: slaclab/std-match

Notes:

Description

adding StdMatch() fucntion to StdRtlPkg.vhd

Allow dontcares in AxiLiteCrossbar config
Author: Larry Ruckman [email protected]
Date: Tue Feb 26 15:13:11 2019 -0800
Pull: #379 (14 additions, 6 deletions, 1 files changed)
Branch: slaclab/axi-xbar

Notes:

This change allows dontcare '-' values for addresses in AxiLiteCrossbar configuration constants.

Description

The AxiLiteCrossbar uses fixed addressing when decoding base addresses. As a consequence, the base address needs to be passed down through generics to any module that instantiates an AxiLiteCrossbar down in the hierarchy. This can be annoying.

This change allows relative addressing when decoding the base address by allowing dontcare values in baseAddr fields.

Example:

constant AXIL_XBAR_CFG_DEFAULT_C : AxiLiteCrossbarMasterConfigArray(0 to 3) := (
      0                  => (
            baseAddr     => X"---00000",
            addrBits     => 16,
            connectivity => X"FFFF"),
      1                  => (
            baseAddr     => X"---10000",
            addrBits     => 16,
            connectivity => X"FFFF"),
      2                  => (
            baseAddr     => X"---20000",
            addrBits     => 16,
            connectivity => X"FFFF"),
      3                  => (
            baseAddr     => X"---30000",
            addrBits     => 16,
            connectivity => X"FFFF"));

Details

This is mostly intended as a stopgap. Using dontcares with hexadecimal formatting means that they always occupy 4 bits each, so base addresses would need to lie of 4-bit boundaries. It works but its not ideal.

Eventually I'd like to rewrite the crossbar config generic with better fields. (We'd get rid of the mostly useless connectivity field too).

AxiStreamBatcher.vhd Update
Author: Larry Ruckman [email protected]
Date: Fri Feb 8 17:37:44 2019 -0800
Pull: #374 (4 additions, 6 deletions, 1 files changed)
Branch: slaclab/AxiStreamBatcher-update

Notes:

Description

  • depreciating lastByteCnt and replacing with WIDTH for SW performance improvement

Note

The revision controlled confluence page got updated today as well:
https://confluence.slac.stanford.edu/display/ppareg/AxiStream+Batcher+Protocol+Version+1

Remove std_ulogic_vector variant of StdMatch()
Author: Benjamin Reese [email protected]
Date: Tue Feb 26 15:14:29 2019 -0800
Pull: #383 (0 additions, 5 deletions, 1 files changed)
Branch: slaclab/std-match

Notes:

Remove a StdMatch overload that was causing a compile error.

Description

This line:

function StdMatch (L, R: std_ulogic_vector) return boolean;

was causing this error:

The following error(s) were detected during synthesis:
 a homograph of stdmatch is already declared in this region [/u/re/bareese/projects/heavy-photon-daq/firmware/submodules/surf/base/general/rtl/StdRtlPkg.vhd:154]
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details

This overloaded StdMatch function has been removed.

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Patch Release

08 Feb 18:41
@ruck314 ruck314
v1.9.6
cfcc587
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Patch Release

Pull Requests

  1. #373 - v1.9.6 release candidate
  2. #371 - New simulation interface to Rogue
  3. #369 - adding Ultrascale GTH PGPv3 @ 3.125 Gb/s support
  4. #367 - AxiStreamBatcherEventBuilder.vhd Update
  5. #370 - Expose RX Equalizer choice in Gtx7Core to users of Pgp2bGtx7FixedLat, Pgp2bGtx7MultiLane, and Pgp2bGtx7VarLat.
  6. #368 - adding EXT_CTRL_ONLY_G to AxiLiteRingBuffer.vhd
  7. #366 - AxiStreamBatcherEventBuilder bug fix

Pull Request Details

v1.9.6 release candidate
Author: Larry Ruckman [email protected]
Date: Fri Feb 8 10:37:02 2019 -0800
Pull: #373 (3120 additions, 751 deletions, 27 files changed)
Branch: slaclab/pre-release

Notes:

Description

  • New simulation interface to Rogue (#371)
  • AxiStreamBatcherEventBuilder bug fix (#366)
  • AxiStreamBatcherEventBuilder.vhd Update for viewing simulation (#367)
  • Expose RX Equalizer choice in Gtx7Core to users of Pgp2bGtx7FixedLat, Pgp2bGtx7MultiLane, and Pgp2bGtx7VarLat (#370)
  • adding Ultrascale GTH PGPv3 @ 3.125 Gb/s support (#369)
  • adding EXT_CTRL_ONLY_G to AxiLiteRingBuffer.vhd (#368)

New simulation interface to Rogue
Author: Larry Ruckman [email protected]
Date: Fri Feb 8 09:58:46 2019 -0800
Pull: #371 (1549 additions, 731 deletions, 14 files changed)
Branch: slaclab/ESROGUE-323_ESROGUE-322
Jira: https://jira.slac.stanford.edu/issues/ESROGUE-323_ESROGUE-322

Notes:

This PR changes the simulation interface between firmware and the Rogue platform. The old RogueStreamSim module goes away and is replaced by the new RogueTcpStream module. This modules interfaces directly the to rogue.interfaces.stream.TcpClient module in Rogue. In order to continue to support sideband signals a RogueSideBand module is available which interfaces to the pyrogue.simulation.interfaces.SideBandSim class. Lastly a new memory bus interface is available in the form a RogueTcpMemory module which interfaces to the rogue.interfaces.memory.TcpClient class in Rogue.

The RogueTcpStreamWrap module has a CHAN_COUNT_G generic which allows interfacing a multiplexed stream in simulation. Each stream requires a matching TcpClient in rogue.

adding Ultrascale GTH PGPv3 @ 3.125 Gb/s support
Author: Larry Ruckman [email protected]
Date: Fri Feb 8 10:29:53 2019 -0800
Pull: #369 (1554 additions, 10 deletions, 7 files changed)
Branch: slaclab/pgpv3-3Gbps

Notes:

Description

  • adding Ultrascale GTH PGPv3 @ 3.125 Gb/s support
  • GTX7 and GTP7 already have this support

AxiStreamBatcherEventBuilder.vhd Update
Author: Larry Ruckman [email protected]
Date: Mon Feb 4 21:17:32 2019 -0800
Pull: #367 (6 additions, 4 deletions, 1 files changed)
Branch: slaclab/AxiStreamBatcherEventBuilder-update

Notes:

Description

  • Reset the accept field (makes it easier to look at simulation)

Expose RX Equalizer choice in Gtx7Core to users of Pgp2bGtx7FixedLat, Pgp2bGtx7MultiLane, and Pgp2bGtx7VarLat.
Author: Larry Ruckman [email protected]
Date: Wed Feb 6 14:51:14 2019 -0800
Pull: #370 (6 additions, 2 deletions, 3 files changed)
Branch: lsst-camera-daq/gtx7_rxeq

Notes:

Expose RX Equalizer choice in Gtx7Core to users of Pgp2bGtx7FixedLat, Pgp2bGtx7MultiLane, and Pgp2bGtx7VarLat.

Description

Gtx7Core provides the ability to select LPM or DFE as the RX Equalizer in the GTX, the 3 PGP2 blocks that use Gtx7Core hardcode this to DFE. COB versions 10 and 11, require LPM to function. These changes just expose the Gtx7Core generic (RX_EQUALIZER_G) to the outside world.

adding EXT_CTRL_ONLY_G to AxiLiteRingBuffer.vhd
Author: Larry Ruckman [email protected]
Date: Fri Feb 8 10:29:32 2019 -0800
Pull: #368 (3 additions, 2 deletions, 1 files changed)
Branch: slaclab/AxiLiteRingBuffer-update

Notes:

Description

  • adding EXT_CTRL_ONLY_G to AxiLiteRingBuffer.vhd
  • Allows the users to get access to the full RAM data (instead of all but the first sample) when doing external control

AxiStreamBatcherEventBuilder bug fix
Author: Larry Ruckman [email protected]
Date: Thu Jan 31 11:05:18 2019 -0800
Pull: #366 (2 additions, 2 deletions, 1 files changed)
Branch: slaclab/AxiStreamBatcherEventBuilder-bug-fix

Notes:

…case

Description

  • AxiStreamBatcherEventBuilder bug fix for superFrameByteThreshold=0x0 case
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31 Jan 05:45
@ruck314 ruck314
v1.9.5
abcf62b
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Pull Requests

  1. #363 - v1.9.5 release candidate
  2. #361 - Microblaze for Vivado 2018.3
  3. #359 - Adding simple unsigned boxcar filter
  4. #365 - v1.9.5 release candidate w/ bug fix
  5. #364 - Pgp3 generic removal patch
  6. #362 - PGPv3 skipInterval bug fix
  7. #360 - python bug fix
  8. #358 - SaltRx bug fix

Pull Request Details

v1.9.5 release candidate
Author: Larry Ruckman [email protected]
Date: Wed Jan 30 15:36:00 2019 -0800
Pull: #363 (2991 additions, 41 deletions, 15 files changed)
Branch: slaclab/pre-release

Notes:

Description

  • SaltRx bug fix (#358)
  • python bug fix for TI devices (#360)
  • Microblaze for Vivado 2018.3 (#361)
  • PGPv3 skipInterval bug fix (#362)
  • Adding simple unsigned boxcar filter (#359)

Microblaze for Vivado 2018.3
Author: Larry Ruckman [email protected]
Date: Mon Jan 28 11:28:55 2019 -0800
Pull: #361 (2701 additions, 2 deletions, 2 files changed)
Branch: slaclab/vivado-2018-3-microblaze

Notes:

Description

  • Updating surf's microblaze for Vivado 2018.3
  • This only required manually editing the .bd file to use Microblaze version 11.0 everywhere we see version 10.0 (Vivado doesn't automatically upgrade this .bd file)

Adding simple unsigned boxcar filter
Author: Larry Ruckman [email protected]
Date: Wed Jan 30 15:28:42 2019 -0800
Pull: #359 (254 additions, 0 deletions, 2 files changed)
Branch: slaclab/boxcar-filter

Notes:

Description

  • Adding simple unsigned boxcar filter

JIRA

ESLMPS-36

v1.9.5 release candidate w/ bug fix
Author: Larry Ruckman [email protected]
Date: Wed Jan 30 21:42:38 2019 -0800
Pull: #365 (10 additions, 73 deletions, 10 files changed)
Branch: slaclab/pre-release

Notes:

Description

  • Fixed broken build (depreciating TX_SKP_INTERVAL_G generic in PGPv3)
  • Fixed borken build (depreciating TX_SKP_BURST_SIZE_G generic in PGPv3 )
  • depreciating RX_ALIGN_GOOD_COUNT_G/RX_ALIGN_BAD_COUNT_G generics in PGPv3

Pgp3 generic removal patch
Author: Larry Ruckman [email protected]
Date: Wed Jan 30 16:22:55 2019 -0800
Pull: #364 (10 additions, 73 deletions, 10 files changed)
Branch: slaclab/pgp3-generic-removal-patch

Notes:

Description

  • Fixed broken build (depreciating TX_SKP_INTERVAL_G generic in PGPv3)
  • Fixed borken build (depreciating TX_SKP_BURST_SIZE_G generic in PGPv3 )
  • depreciating RX_ALIGN_GOOD_COUNT_G/RX_ALIGN_BAD_COUNT_G generics in PGPv3

PGPv3 skipInterval bug fix
Author: Larry Ruckman [email protected]
Date: Wed Jan 30 13:49:25 2019 -0800
Pull: #362 (27 additions, 30 deletions, 7 files changed)
Branch: slaclab/pgp3-skip-interval-bug-fix

Notes:

Description

  • bug fix for dynamic pgpTxIn.skpInterval config
  • updaing PGP3_TX_IN_INIT_C.skpInterval non-zero (required to prevent the skpInterval=0 when EN_PGP_MON_G=true)

python bug fix
Author: Larry Ruckman [email protected]
Date: Thu Jan 24 12:24:04 2019 -0800
Pull: #360 (8 additions, 8 deletions, 3 files changed)
Branch: slaclab/python-surf-devices-ti

Notes:

Description

  • python bug fix

SaltRx bug fix
Author: Larry Ruckman [email protected]
Date: Fri Jan 18 11:26:15 2019 -0800
Pull: #358 (1 additions, 1 deletions, 1 files changed)
Branch: slaclab/SaltRx-bug-fix

Notes:

Description

  • SaltRx bug fix
  • related to increasing the AXIS bus width support to larger than 128-bit
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Patch Release

15 Jan 16:42
@ruck314 ruck314
v1.9.4
04fc61f
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Pull Requests

  1. #355 - v1.9.4 release candidate
  2. #354 - Working Cameralink Library
  3. #352 - Add store and forward buffer in SRPv3 TX FIFO path
  4. #353 - Fix error in dma write engine related to back to back frames on the same VC
  5. #351 - AxiDualPortRam Bug Fix
  6. #356 - Update LICENSE.txt

Pull Request Details

v1.9.4 release candidate
Author: Larry Ruckman [email protected]
Date: Tue Jan 15 08:39:47 2019 -0800
Pull: #355 (117 additions, 75 deletions, 10 files changed)
Branch: slaclab/pre-release

Notes:

Description

  • AxiDualPortRam Bug Fix (#351)
  • Add store and forward buffer in SRPv3 TX FIFO path (#352)
  • Fix error in dma write engine related to back to back frames on the same VC (#353)
  • Working Cameralink Library (#354)

Working Cameralink Library
Author: Larry Ruckman [email protected]
Date: Mon Jan 14 14:32:52 2019 -0800
Pull: #354 (73 additions, 47 deletions, 6 files changed)
Branch: slaclab/clink_fixes

Notes:

Tested and working with new cameralink to PGP board.

Add store and forward buffer in SRPv3 TX FIFO path
Author: Larry Ruckman [email protected]
Date: Mon Jan 14 09:56:04 2019 -0800
Pull: #352 (13 additions, 11 deletions, 1 files changed)
Branch: slaclab/ESCORE-407
Jira: https://jira.slac.stanford.edu/issues/ESCORE-407

Notes:

Description

  • Add store and forward buffer in SRPv3 TX FIFO path
  • This would avoid sending partial frames upstream while the transaction is still in progress.

JIRA

ESCORE-407

Fix error in dma write engine related to back to back frames on the same VC
Author: Larry Ruckman [email protected]
Date: Mon Jan 14 12:05:41 2019 -0800
Pull: #353 (16 additions, 7 deletions, 1 files changed)
Branch: slaclab/ESCORE-408
Jira: https://jira.slac.stanford.edu/issues/ESCORE-408

Notes:

Recent timing optimizations in the dma write engine have exposed a bug that occurs under the following conditions:

  1. Back to back frames with the same dest
  2. Frame size exactly matches the dma transaction size.

In this case the dma engine would incorrectly detect that the incoming frame is a continuation of the previous frame. This causes both data errors and caused the dma engine to loose track of the dma buffers.

AxiDualPortRam Bug Fix
Author: Larry Ruckman [email protected]
Date: Mon Jan 14 07:47:32 2019 -0800
Pull: #351 (14 additions, 9 deletions, 1 files changed)
Branch: slaclab/AxiDualPortRam-bug-fix

Notes:

Description

  • AxiDualPortRam Bug Fix

History

Matthias was using this configuration ....

   U_LUT : entity work.AxiDualPortRam
      generic map (
         TPD_G            => TPD_G,
         REG_EN_G         => false,
         AXI_WR_EN_G      => true,
         SYS_WR_EN_G      => false,
         SYS_BYTE_WR_EN_G => false,
         COMMON_CLK_G     => true,
         ADDR_WIDTH_G     => 10,
         DATA_WIDTH_G     => 32)
      port map (
         -- Axi Port
         axiClk         => clk160MHz,
         axiRst         => rst160MHz,
         axiReadMaster  => axilReadMasters(LUT_INDEX_C),
         axiReadSlave   => axilReadSlaves(LUT_INDEX_C),
         axiWriteMaster => axilWriteMasters(LUT_INDEX_C),
         axiWriteSlave  => axilWriteSlaves(LUT_INDEX_C),
         -- Standard Port
         clk            => clk160MHz,
         addr           => ramAddr,
         dout           => ramData);

... and discovered that only the first word in the BRAM would read/write from software. The other words would also return. After doing a VCS simulation, I go this error message:

Error-[SIMERR_ASOOB_VALUE_SCOPE] Invalid Array Index
/u/re/ruckman/projects/atlas/atlas-rd53-daq/firmware/submodules/surf/axi/axi-lite/rtl/AxiDualPortRam.vhd, 276
                    v.axiWrStrobe((decAddrInt+1)*4-1 downto decAddrInt*4) :=
  Array subscript 4 out of bounds (3 downto 0)
  in scope: /ATLASRD53FEBTB/U_FEB/U_HITTRIG/U_LUT/COMB at 73665401 PS from 
  process /ATLASRD53FEBTB/U_FEB/U_HITTRIG/U_LUT/COMB.
  Please extend the bounds in the array definition or ensure that the 
  subscript is within the defined bounds.

I add more constants to make it easier to see what the integer subtypes were configured as in simulation (subtype configurations don't show up in Vivado XSIM or VCS) and then fixed this firmware module for Matthias case

Update LICENSE.txt
Author: Larry Ruckman [email protected]
Date: Tue Jan 15 08:29:02 2019 -0800
Pull: #356 (1 additions, 1 deletions, 1 files changed)
Branch: slaclab/ruck314-patch-1

Notes:

Description

Update LICENSE.txt for 2019 copyright

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Patch Release

29 Nov 18:30
@ruck314 ruck314
v1.9.3
b156326
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Pull Requests

  1. #348 - v1.9.3 release candidate
  2. #345 - Fix VCS compile error
  3. #343 - Remove buffer base address
  4. #344 - Fixed width mismatch when OUTPUT_BUFG_G=false
  5. #346 - Fix bad descriptor return
  6. #349 - studder step flow control bug fix to AxiRam.vhd
  7. #347 - Fix bad address decode for write index

Pull Request Details

v1.9.3 release candidate
Author: Larry Ruckman [email protected]
Date: Thu Nov 29 10:26:19 2018 -0800
Pull: #348 (48 additions, 49 deletions, 5 files changed)
Branch: slaclab/pre-release

Notes:

Description

  • AxiStreamDmaV2: Remove buffer base address (#343)
  • ClockManager7: Fixed width mismatch when OUTPUT_BUFG_G=false (#344)
  • AxiStreamDmaV2: Fix bad descriptor return (#346)
  • AxiStreamDmaV2: Fix bad address decode for write index (#347)
  • AxiStreamPacketizer: Fix VCS compile error (#345)
  • AxiRam.vhd: studder step flow control bug fix (#349)

Fix VCS compile error
Author: Larry Ruckman [email protected]
Date: Thu Nov 29 07:47:38 2018 -0800
Pull: #345 (34 additions, 34 deletions, 2 files changed)
Branch: slaclab/vcs-fix

Notes:

Description

VCS didn't like the way a constant was being assigned. You can't do:
(0 => '1', others =>'0')

Vivado allows it but it is technically illegal VHDL. VCS is overly pedantic about these things.

Remove buffer base address
Author: Larry Ruckman [email protected]
Date: Thu Nov 15 08:39:47 2018 -0800
Pull: #343 (4 additions, 7 deletions, 1 files changed)
Branch: slaclab/dma_update

Notes:

Description

The base address register is not required for normal operation. Instead the driver is setup to limit the allocated address range.

Fixed width mismatch when OUTPUT_BUFG_G=false
Author: Larry Ruckman [email protected]
Date: Tue Nov 20 15:03:43 2018 -0800
Pull: #344 (6 additions, 4 deletions, 1 files changed)
Branch: slaclab/mmcm-fix

Notes:

Description

I found and fixed a width mismatch bug when disabling output BUFG insertion.

Fix bad descriptor return
Author: Larry Ruckman [email protected]
Date: Mon Nov 26 15:39:01 2018 -0800
Pull: #346 (2 additions, 2 deletions, 1 files changed)
Branch: slaclab/bad_ret

Notes:

Description

The wrong descriptor data was being returned on writes.

studder step flow control bug fix to AxiRam.vhd
Author: Larry Ruckman [email protected]
Date: Thu Nov 29 10:24:57 2018 -0800
Pull: #349 (1 additions, 1 deletions, 1 files changed)
Branch: slaclab/AxiRam-bug-fix

Notes:

Description

studder step flow control bug fix to AxiRam.vhd

Fix bad address decode for write index
Author: Larry Ruckman [email protected]
Date: Tue Nov 27 16:00:40 2018 -0800
Pull: #347 (1 additions, 1 deletions, 1 files changed)
Branch: slaclab/bad_ret

Notes:

Description

Write index was being decoded improperly.

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Patch Release

12 Nov 20:13
@ruck314 ruck314
v1.9.2
2fbb06e
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Pull Requests

  1. #341 - v1.9.2 release candidate
  2. #340 - Doxygen + Travis CI Integration
  3. #342 - Fix doc script

Pull Request Details

v1.9.2 release candidate
Author: Larry Ruckman [email protected]
Date: Fri Nov 9 14:24:47 2018 -0800
Pull: #341 (272 additions, 62 deletions, 6 files changed)
Branch: slaclab/pre-release

Notes:

Description

  • Doxygen + Travis CI Integration (#340)

Doxygen + Travis CI Integration
Author: Larry Ruckman [email protected]
Date: Fri Nov 9 12:14:10 2018 -0800
Pull: #340 (272 additions, 62 deletions, 6 files changed)
Branch: slaclab/doxygen-travis-ci

Notes:

Description

  • Doxygen + Travis CI Integration

Fix doc script
Author: Larry Ruckman [email protected]
Date: Fri Nov 9 16:23:05 2018 -0800
Pull: #342 (1 additions, 1 deletions, 1 files changed)
Branch: slaclab/fix-doc-script

Notes:

Description

Fix generateDocumenationAndDeploy.sh script to avoid it to return an error code which makes travis to fail.

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Patch Release

08 Nov 23:59
@ruck314 ruck314
v1.9.1
8d13245
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Pull Requests

  1. #339 - v1.9.1 release candidate
  2. #336 - Removing the "broken" floating point source code
  3. #337 - python bug fix for Si5345.py
  4. #338 - [email protected] bug fix for AxiStreamDmaRingWrite

Pull Request Details

v1.9.1 release candidate
Author: Larry Ruckman [email protected]
Date: Thu Nov 8 15:55:01 2018 -0800
Pull: #339 (6 additions, 1301 deletions, 13 files changed)
Branch: slaclab/pre-release

Notes:

Description

  • python bug fix (#337)
  • VHDL bug fix (#338)
  • Removing the "broken" floating point source code (#336)

Removing the "broken" floating point source code
Author: Larry Ruckman [email protected]
Date: Thu Nov 8 15:54:52 2018 -0800
Pull: #336 (2 additions, 1298 deletions, 11 files changed)
Branch: slaclab/ESCORE-242
Jira: https://jira.slac.stanford.edu/issues/ESCORE-242

Notes:

Description

  • Removing the floating point source code
  • Only works for simulation and not synthesis
  • Hopefully Vivado will fix this issue and more VHDL-2008 support in a later version

JIRA

ESCORE-242

python bug fix for Si5345.py
Author: Larry Ruckman [email protected]
Date: Thu Nov 8 14:53:59 2018 -0800
Pull: #337 (2 additions, 2 deletions, 1 files changed)
Branch: slaclab/atlas-altiroc-dev

Notes:

Description

python bug fix

[email protected] bug fix for AxiStreamDmaRingWrite
Author: Larry Ruckman [email protected]
Date: Thu Nov 8 14:54:08 2018 -0800
Pull: #338 (2 additions, 1 deletions, 1 files changed)
Branch: slaclab/AxiStreamDmaRingWrite

Notes:

Description

[email protected] bug fix

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Minor Release

07 Nov 17:19
@ruck314 ruck314
v1.9.0
d616323
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Pull Requests

  1. #313 - v1.9.0 release candidate
  2. #301 - Adding PGPv3 support for GTP7
  3. #293 - Remove Created and Last update comment header lines
  4. #308 - Si5345 Support
  5. #289 - Adding Ultrascale support for Ad9249
  6. #304 - Updated AXI Stream from 128-bit to 512-bit
  7. #303 - removing obsolete source code
  8. #306 - Misc. Updates for EPIX Development
  9. #281 - exposing ETH pause generic configurations
  10. #331 - IP Bus to AXI-Lite bridge and AXI-Lite to IP Bus bridge
  11. #334 - Updates to SURF from ATLAS ALTIROC development
  12. #283 - removing duplicated code that's used in both UltraScale and UltraScale+
  13. #312 - Apply fixes to yaml files needed for CPSW tools
  14. #296 - ADC32RF45 and RssiWrapper Updates
  15. #329 - Support for 128bit descriptors in DMA engine.
  16. #327 - Adding AxiRam and its simulation testbed
  17. #300 - Asynchronous Gearbox
  18. #282 - Update for LMK/DAC init sequence for cryo, use pulsed SysRef
  19. #294 - AxiStream Batcher Version1
  20. #309 - Remove AxiStreamPacketizerMux
  21. #292 - Rogue device tweaks
  22. #291 - Add a generic Gearbox module
  23. #330 - Adding inferred RAM support to AxiRam.vhd
  24. #280 - I2C Cleanup
  25. #316 - Add AxiStreamRepeater.vhd
  26. #288 - Re-coding axiSlaveRegister to not use recursion
  27. #279 - Propagate RSSI Segment Size to the Packetizer
  28. #298 - Depreciating surf.misc.GenericMemory.py
  29. #332 - Depreciating AxiStreamBatcherEventBuilder's Event Interface
  30. #311 - adding SyncTrigPeriod.vhd
  31. #299 - deprecating the optional mAxisMaster interface
  32. #273 - bug fix to TX gmii preamble
  33. #322 - RSSI: Connecting RX buffer full to RssiMonitor.vhd
  34. #290 - updating linkrate and linkwidth to LinkVariables
  35. #310 - migrating from GenericMemory to MemoryDevice
  36. #268 - removing location constraints in the .DCP files
  37. #270 - corner case bug fix for AxiMicronN25Q.py
  38. #328 - Add arprot/awprot support to SRPv3
  39. #315 - SyncTrigPeriod.vhd Bug fix
  40. #271 - Catch read error in AxiVersion
  41. #284 - Make axiSlaveRegisterR() ignore write requests instead of responding with OK
  42. #305 - Add option to run XADC DRP at a different clock than axilClk
  43. #333 - Resolved Vivado syntax warnings and critical warning messages for SURF's I2C lib
  44. #262 - depreciating unused AXI stream interface
  45. #325 - fix the python file names to CamalCase
  46. #276 - Fix VCS warning due to use other (others => ...)
  47. #277 - Add notes for setting gtx7 clocks
  48. #324 - Resolved null assignment in AxiDualPortRam.vhd
  49. #314 - Python devices.ti Update
  50. #287 - fixed false output transition after reset
  51. #326 - Fixed broken SRPv3AxiLiteFull.vhd module
  52. #272 - Update PyRogue
  53. #318 - Bad descriptor return size for read buffers
  54. #274 - Fix mismatched function declaration
  55. #295 - Lmk04828.py Update
  56. #286 - fixing genAxiLiteConfig declaration
  57. #317 - Bad size constant for AxiWriteDmaDescAckType
  58. #307 - Fix comma in python
  59. #302 - Fix 8-byte fixed size in endianSwap()
  60. #285 - Dac38J84.py bug fix
  61. #319 - Cut and paste error

Pull Request Details

v1.9.0 release candidate
Author: Larry Ruckman [email protected]
Date: Tue Nov 6 11:10:26 2018 -0800
Pull: #313 (18650 additions, 7932 deletions, 708 files changed)
Branch: slaclab/pre-release

Notes:

Description

  • Major Change: Updated AXI Stream from 128-bit to 512-bit (#304)
  • bug fix to TX gmii preamble (#273)
  • removing location constraints in the .DCP files (#268)
  • depreciating unused AXI stream interface (#262)
  • corner case bug fix for AxiMicronN25Q.py (#270)
  • Fix mismatched function declaration (#274)
  • Fix VCS warning due to use other (others => ...) (#276)
  • Add notes for setting gtx7 clocks (#277)
  • Update for LMK/DAC init sequence for cryo, use pulsed SysRef (#282)
  • Dac38J84.py bug fix (#285)
  • fixing genAxiLiteConfig declaration (#286)
  • fixed false output transition after reset (#287)
  • I2C Cleanup (#280)
  • removing duplicated code that's used in both UltraScale and UltraScale+ (#283)
  • exposing ETH pause generic configurations (#281)
  • Adding Ultrascale support for Ad9249 (#289)
  • Re-coding axiSlaveRegister to not use recursion (#288)
  • updating linkrate and linkwidth to LinkVariables for AxiPciePhy.py (#290)
  • Remove Created and Last update comment header lines (#293)
  • Rogue device tweaks (#292)
  • Add a generic Gearbox module (#291)
  • Fix 8-byte fixed size in endianSwap (#302)
  • Adding Asynchronous Gearbox (#300)
  • deprecating the optional mAxisMaster interface for SsiPrbsRx.vhd (#299)
  • Added AxiStream Batcher Version1 (#294)
  • Fix comma in python (#307)
  • Add option to run XADC DRP at a different clock than axilClk (#305)
  • Remove AxiStreamPacketizerMux (#309)
  • removing obsolete source code (#303)
  • Depreciating surf.misc.GenericMemory.py (#298)
  • Misc. Updates for EPIX Development (#306)
  • Make axiSlaveRegisterR() ignore write requests instead of responding with OK (#284)
  • Si5345 Support (#308)
  • Lmk04828.py Update (#295)
  • Adding PGPv3 support for GTP7 (#301)
  • ADC32RF45 and RssiWrapper Updates (#296)
  • migrating from GenericMemory to MemoryDevice (#310)
  • Apply fixes to yaml files needed for CPSW tools (#312)
  • Catch read error in AxiVersion (#272)
  • adding SyncTrigPeriod.vhd (#311)
  • Propagate RSSI Segment Size to the Packetizer (#279)
  • Connecting RX buffer full to RssiMonitor.vhd (#322)
  • Adding AxiRam and its simulation testbed (#327)
  • Add arprot/awprot support to SRPv3 (#328)
  • fix the python file names to CamalCase (#325)
  • Resolved null assignment in AxiDualPortRam.vhd (#324)
  • IP Bus to AXI-Lite bridge and AXI-Lite to IP Bus bridgeAxiDualPortRam.vhd (#331)
  • Support for 128bit descriptors in DMA engine (#329)
  • Resolved Vivado syntax warnings and critical warning messages for SURF's I2C lib (#333)
  • Adding inferred RAM support to AxiRam.vhd (#330)
  • Fixed broken SRPv3AxiLiteFull.vhd module (#326)
  • Updates to SURF from ATLAS ALTIROC development (#334)

Adding PGPv3 support for GTP7
Author: Larry Ruckman [email protected]
Date: Thu Oct 11 16:30:58 2018 -0700
Pull: #301 (4923 additions, 63 deletions, 27 files changed)
Branch: slaclab/PGPv3-gtp7

Notes:

Description

  • Adding PGPv3 support for GTP7
  • Fixed a rounding error in MmcmEmulation.vhd
  • Fixed a bug in MmcmEmulation.vhd that would lock up during the phasing up process if clock stops and RST=0x1

Remove Created and Last update comment header lines
Author: Benjamin Reese [email protected]
Date: Tue Sep 18 11:24:12 2018 -0700
Pull: #293 (1069 additions, 2193 deletions, 575 files changed)
Branch: slaclab/rem-update-date

Notes:

The lines with

-- Created    : xxx
-- Last update: xxx

Were tending to cause merge conflicts.

Git tracks this info anyway, so I wrote a script to remove them from every *.vhd file.

The script also changed everything to Unix style line endings if it wasn't already.

Si5345 Support
Author: Benjamin Reese [email protected]
Date: Thu Oct 11 16:18:55 2018 -0700
Pull: #308 (2999 additions, 0 deletions, 6 files changed)
Branch: slaclab/Si5345-dev

Notes:

Description

  • Adding Si5345 Support support
  • Added InputBufferReg/OutputBufferReg for 7 series

Adding Ultrascale support for Ad9249
Author: Benjamin Reese [email protected]
Date: Tue Sep 11 16:06:32 2018 -0700
Pull: #289 (1843 additions, 69 deletions, 17 files changed)
Branch: slaclab/ad9249Ultrascale

Notes:

Description

  • Adding Ultrascale support for Ad9249

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