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Releases: slaclab/surf

Patch Release

03 Aug 15:34
@ruck314 ruck314
v1.8.9
f04df28
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Patch Release

Pull Requests

  1. #267 - v1.8.9 release candidate
  2. #263 - Added Transceiver Debug Interface to TenGigEthGtx7Core
  3. #258 - AXI4: Breaking apart long combinatorial chain in awlen/arlen calculation
  4. #266 - ETH: DHCP Update

Pull Request Details

v1.8.9 release candidate
Author: Larry Ruckman [email protected]
Date: Fri Aug 3 08:31:34 2018 -0700
Pull: #267 (200 additions, 53 deletions, 9 files changed)
Branch: slaclab/pre-release

Notes:

Description

  • Added Transceiver Debug Interface to TenGigEthGtx7Core (#263)
  • AXI4: Breaking apart long combinatorial chain in awlen/arlen calculation (#258)
  • ETH: DHCP Update (#266)

Added Transceiver Debug Interface to TenGigEthGtx7Core
Author: Larry Ruckman [email protected]
Date: Wed Aug 1 16:41:30 2018 -0700
Pull: #263 (89 additions, 27 deletions, 5 files changed)
Branch: slaclab/ESCORE-367
Jira: https://jira.slac.stanford.edu/issues/ESCORE-367

Notes:

Description

  • Added Transceiver Debug Interface to TenGigEthGtx7Core
  • Setting the extRst to default of '0'

JIRA

ESCORE-367

AXI4: Breaking apart long combinatorial chain in awlen/arlen calculation
Author: Larry Ruckman [email protected]
Date: Wed Aug 1 16:41:52 2018 -0700
Pull: #258 (85 additions, 9 deletions, 3 files changed)
Branch: slaclab/ESCORE-360
Jira: https://jira.slac.stanford.edu/issues/ESCORE-360

Notes:

Description

  • Breaking apart long combinatorial chain in awlen/arlen calculation

JIRA

ESCORE-360

ETH: DHCP Update
Author: Larry Ruckman [email protected]
Date: Fri Aug 3 08:27:47 2018 -0700
Pull: #266 (26 additions, 17 deletions, 1 files changed)
Branch: slaclab/ESCORE-369
Jira: https://jira.slac.stanford.edu/issues/ESCORE-369

Notes:

Description

  • Added "Endmark" to Discover and Request messages (required for CISCO and Apple DHCP)
  • Fixed bug of HOPS!=0 causing dropps DHCP offer/ACK messages
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Patch Release

01 Aug 23:40
@ruck314 ruck314
v1.8.8
c4d7f2b
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Patch Release

Pull Requests

  1. #265 - v1.8.8 release candidate
  2. #255 - RSSI Update
  3. #264 - Fixed AxiStreamPacketizer2 CRC Bug
  4. #261 - GigEthGthUltraScaleCore Update
  5. #260 - adding configuration checking to AxiLitePkg.genAxiLiteConfig()

Pull Request Details

v1.8.8 release candidate
Author: Larry Ruckman [email protected]
Date: Wed Aug 1 16:38:11 2018 -0700
Pull: #265 (185 additions, 65 deletions, 6 files changed)
Branch: slaclab/pre-release

Notes:

Description

  • RSSI Update (#255)
  • Added configuration checking to AxiLitePkg.genAxiLiteConfig() (#260)
  • GigEthGthUltraScaleCore Update (#261)
  • AxiStreamPacketizer2 Bug Fix (#264)

RSSI Update
Author: Larry Ruckman [email protected]
Date: Mon Jul 30 20:18:12 2018 -0700
Pull: #255 (53 additions, 50 deletions, 2 files changed)
Branch: slaclab/rssi-dev

Notes:

Description

  • Added BYP_TX_BUFFER_G/BYP_RX_BUFFER_G generics and optimizing FIFO settings

Fixed AxiStreamPacketizer2 CRC Bug
Author: Larry Ruckman [email protected]
Date: Wed Aug 1 16:37:36 2018 -0700
Pull: #264 (53 additions, 10 deletions, 2 files changed)
Branch: slaclab/ESCORE-368
Jira: https://jira.slac.stanford.edu/issues/ESCORE-368

Notes:

Description

  • fixed AxiStreamPacketizer2 CRC bug

Note

This bug got exposed after this previous bug fix:
78d17fb#diff-1ddf0c59e774cc5f8b1a50f39af03109

JIRA

ESCORE-368

GigEthGthUltraScaleCore Update
Author: Larry Ruckman [email protected]
Date: Tue Jul 24 15:52:31 2018 -0700
Pull: #261 (49 additions, 2 deletions, 1 files changed)
Branch: slaclab/ESCRYODET-149
Jira: https://jira.slac.stanford.edu/issues/ESCRYODET-149

Notes:

Description

  • Defining the component for GigEthGthUltraScaleCore
    -- instead of using entity work.XXXXX. Vivado is complaining without it

JIRA

ESCRYODET-149

adding configuration checking to AxiLitePkg.genAxiLiteConfig()
Author: Larry Ruckman [email protected]
Date: Thu Jul 26 11:40:35 2018 -0700
Pull: #260 (30 additions, 3 deletions, 1 files changed)
Branch: slaclab/ESCORE-365
Jira: https://jira.slac.stanford.edu/issues/ESCORE-365

Notes:

Description

adding configuration checking to AxiLitePkg.genAxiLiteConfig()

JIRA

ESCORE-365

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Patch Release

19 Jul 21:56
@ruck314 ruck314
v1.8.7
3cc5fc7
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Patch Release

Pull Requests

  1. #259 - v1.8.7 release candidate
  2. #254 - Fix last size calculation in packetizer V2

Pull Request Details

v1.8.7 release candidate
Author: Larry Ruckman [email protected]
Date: Thu Jul 19 14:54:25 2018 -0700
Pull: #259 (1 additions, 1 deletions, 1 files changed)
Branch: slaclab/pre-release

Notes:

Description

Bug fix for AxiStreamPacketizer2's tLast calculation

Fix last size calculation in packetizer V2
Author: Larry Ruckman [email protected]
Date: Wed Jul 11 12:47:14 2018 -0700
Pull: #254 (1 additions, 1 deletions, 1 files changed)
Branch: slaclab/ESCRYODET-146
Jira: https://jira.slac.stanford.edu/issues/ESCRYODET-146

Notes:

The current last size calculation does not filter out the upper unused tkeep bits.

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Patch Release

29 Jun 20:37
@ruck314 ruck314
v1.8.6
23134a0
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Patch Release

Pull Requests

  1. #253 - v1.8.6 release candidate
  2. #248 - AXI Simulation Cleanup
  3. #245 - RogueSim and VCS Simulation Updates
  4. #246 - Added password locking ability to Micron PROM devices
  5. #250 - Fix vhpi vector size
  6. #252 - I2c mux lock
  7. #244 - Update axi/simlink/src/Makefile update

Pull Request Details

v1.8.6 release candidate
Author: Larry Ruckman [email protected]
Date: Fri Jun 29 13:35:04 2018 -0700
Pull: #253 (1021 additions, 5184 deletions, 57 files changed)
Branch: slaclab/pre-release

Notes:

Description

  • Update axi/simlink/src/Makefile update (#244)
  • RogueSim and VCS Simulation Updates (#245)
  • AXI Simulation Cleanup (#248)
  • Fix vhpi vector size (#250)
  • Added password locking ability to Micron PROM devices (#246)
  • Adding OVERRIDE_SUBMODULE_LOCKS support (#246)
  • Updating I2c mux lock (#252)

AXI Simulation Cleanup
Author: Larry Ruckman [email protected]
Date: Tue Jun 26 14:59:50 2018 -0700
Pull: #248 (40 additions, 4801 deletions, 37 files changed)
Branch: slaclab/sim-cleanup

Notes:

  1. Remove old simulation software and vhdl which is out of date and no longer used.
  2. Add additional debugging to the rogue simulation interface.

RogueSim and VCS Simulation Updates
Author: Larry Ruckman [email protected]
Date: Mon Jun 25 10:59:52 2018 -0700
Pull: #245 (854 additions, 320 deletions, 11 files changed)
Branch: slaclab/rogue-sim-wrapper

Notes:

Description

  • Renamed RoguePgpSim to RoguePgp2bSim and moved from axi to pgp2b directory
  • Added RoguePgp3Sim.vhd
  • Integrated RoguePgp3Sim into Pgp3Gtx7Wrapper/Pgp3GthUsWrapper
  • Updated axi/simlink/src/Makefile for Ubuntu support
  • Added MmcmEmulation and integrated it into our clock manager wrappers

Added password locking ability to Micron PROM devices
Author: Larry Ruckman [email protected]
Date: Fri Jun 29 09:31:13 2018 -0700
Pull: #246 (99 additions, 43 deletions, 7 files changed)
Branch: slaclab/prom-dev

Notes:

Description

  • Added password locking ability to Micron PROM devices
  • Adding OVERRIDE_SUBMODULE_LOCKS support

Fix vhpi vector size
Author: Larry Ruckman [email protected]
Date: Wed Jun 27 15:56:55 2018 -0700
Pull: #250 (31 additions, 36 deletions, 3 files changed)
Branch: slaclab/ESROGUE-263
Jira: https://jira.slac.stanford.edu/issues/ESROGUE-263

Notes:

I2c mux lock
Author: Larry Ruckman [email protected]
Date: Fri Jun 29 12:40:09 2018 -0700
Pull: #252 (23 additions, 3 deletions, 2 files changed)
Branch: slaclab/i2c-mux-lock

Notes:

Description

  • Respond with fail code if an input attempts to access while a different input has a lock on the bus

Update axi/simlink/src/Makefile update
Author: Larry Ruckman [email protected]
Date: Wed Jun 20 14:18:41 2018 -0700
Pull: #244 (14 additions, 4 deletions, 1 files changed)
Branch: slaclab/vcs-dev

Notes:

Description

Adding licensing header and Ubuntu support

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Patch Release

22 Jun 00:13
@ruck314 ruck314
v1.8.5
a35ab97
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Patch Release

Pull Requests

  1. #241 - v1.8.5 release candidate
  2. #239 - PGPv3 Updates
  3. #237 - PGPv3: GTX7 Update
  4. #232 - Including local busy into RSSI's header
  5. #242 - adding zynquplus support to surf
  6. #221 - New UART Features
  7. #238 - SsiPrbsRx Update
  8. #235 - Seperate cache settings in Axis gen2 DMA
  9. #233 - Fix natural range spec outside of max bounds
  10. #236 - GTX7's QPLL Bug Fix
  11. #234 - Add xvcSrv to .gitignore

Pull Request Details

v1.8.5 release candidate
Author: Larry Ruckman [email protected]
Date: Thu Jun 21 16:55:08 2018 -0700
Pull: #241 (2275 additions, 456 deletions, 55 files changed)
Branch: slaclab/pre-release

Notes:

Description

  • Fixed flow control bug in AxiStreamPacketizer2.vhd
  • Fixed overflow synchronization issue
  • Updated python to match FW error counter size
  • Added pause/overflow event message sending to PGPv3 TX protocol
  • Added SOF check to SsiPrbsRx
  • Updated AXIS flow control procedure to SsiPrbsRx
  • Added 3.125Gbps support to PGPv3 GTX7
  • GTX7's QPLL Bug Fix
  • Seperate cache settings in Axis gen2 DMA
  • Add xvcSrv to .gitignore
  • Including local busy into RSSI's header
  • UART Updates (#221)
  • Added zynquplus support

PGPv3 Updates
Author: Larry Ruckman [email protected]
Date: Thu Jun 14 08:45:08 2018 -0700
Pull: #239 (1789 additions, 127 deletions, 26 files changed)
Branch: slaclab/pgp3-overflow

Notes:

Description

  • Fixed flow control bug in AxiStreamPacketizer2.vhd
  • Fixed overflow synchronization issue
  • Updated python to match FW error counter size
  • Added pause/overflow event message sending to PGPv3 TX protocol

PGPv3: GTX7 Update
Author: Larry Ruckman [email protected]
Date: Tue Jun 12 14:32:35 2018 -0700
Pull: #237 (1616 additions, 34 deletions, 12 files changed)
Branch: slaclab/PGPv3-gtx7-update

Notes:

Description

Adding 3.125Gbps support to PGPv3 GTX7

Including local busy into RSSI's header
Author: Larry Ruckman [email protected]
Date: Tue May 22 14:36:31 2018 -0700
Pull: #232 (176 additions, 82 deletions, 10 files changed)
Branch: slaclab/rssi-busy

Notes:

Description

Including local busy into RSSI's header

adding zynquplus support to surf
Author: Larry Ruckman [email protected]
Date: Mon Jun 18 13:37:09 2018 -0700
Pull: #242 (90 additions, 99 deletions, 8 files changed)
Branch: slaclab/zynquplus

Notes:

Description

Adding zynquplus support to surf

New UART Features
Author: Larry Ruckman [email protected]
Date: Thu Jun 14 12:36:55 2018 -0700
Pull: #221 (117 additions, 48 deletions, 4 files changed)
Branch: slaclab/uart-dev

Notes:

Description

Added generic for enabling the parity bit.

  • PARITY_EN_G : integer range 0 to 1 := 0;

Added generic for selecting parity.

  • PARITY_G : string := "NONE";
  • Options are: "NONE", "EVEN", "ODD"

Added generic for selecting data-width of 5, 6, 7, or 8.

  • DATA_WIDTH_G : integer range 5 to 8 := 8;

Added extra state (PARITY_S) in UartRX.vhd for parity checking.

SsiPrbsRx Update
Author: Larry Ruckman [email protected]
Date: Wed Jun 13 11:45:00 2018 -0700
Pull: #238 (65 additions, 73 deletions, 1 files changed)
Branch: slaclab/SsiPrbsRx

Notes:

Description

  1. Added SOF check
  2. Updated AXIS flow control procedure

JIRA

ESCORE-355

Seperate cache settings in Axis gen2 DMA
Author: Larry Ruckman [email protected]
Date: Thu May 31 15:41:07 2018 -0700
Pull: #235 (26 additions, 16 deletions, 3 files changed)
Branch: slaclab/ESCORE-354
Jira: https://jira.slac.stanford.edu/issues/ESCORE-354

Notes:

This PR will add a separate buffer cache settings for the AXIS gen2 DMA engine. This is required because the proper value for the rd cache bits is different than the write setting.

Fix natural range spec outside of max bounds
Author: Benjamin Reese [email protected]
Date: Tue May 22 14:34:32 2018 -0700
Pull: #233 (10 additions, 10 deletions, 1 files changed)
Branch: slaclab/WatchDogRst-fix

Notes:

Description

Range specified for DURATION_G was greater than max 'natural'.
Removed the range spec since it was redundant anyway.

GTX7's QPLL Bug Fix
Author: Larry Ruckman [email protected]
Date: Fri Jun 8 11:22:35 2018 -0700
Pull: #236 (1 additions, 1 deletions, 1 files changed)
Branch: slaclab/gtx7-update

Notes:

Description

Based on UG476 (v1.12), setting BGRCALOVRD to 5'b11111
"Reserved. This port must be set to 5'b11111. This value should not be modified."

Add xvcSrv to .gitignore
Author: Benjamin Reese [email protected]
Date: Wed May 23 13:01:36 2018 -0700
Pull: #234 (1 additions, 0 deletions, 1 files changed)
Branch: slaclab/xvcSrv-ignore

Notes:

Description

Compiled xvcSrv binary causes dirty build flag if not ignored by git.

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Patch Release

17 May 18:03
@ruck314 ruck314
v1.8.4
916b0e9
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Patch Release

Pull Requests

  1. #228 - v1.8.4 release candidate
  2. #225 - python update for overlapping variables
  3. #227 - AxiStreamDepacketizer2 Flow Control Bug Fix
  4. #229 - Add 'saci' to naming of things to avoid name conflicts
  5. #230 - adding Vivado version checking to protocols/jtag/ruckus.tcl
  6. #231 - Update to SRV3AxiLite
  7. #226 - Update _Dac38J84.py

Pull Request Details

v1.8.4 release candidate
Author: Larry Ruckman [email protected]
Date: Thu May 17 10:58:28 2018 -0700
Pull: #228 (822 additions, 1685 deletions, 25 files changed)
Branch: slaclab/pre-release

Notes:

Description

  1. AxiStreamDepacketizer2 flow control bug fix
  2. Overhauled the RssiCoreTb
  3. Added fifoWrCnt port to AxiStreamFifoV2.vhd
    • Required for applications that have more than 2 FIFO thresholds)
  1. SsiFrameLimiter now checks for double SOF in a frame
  2. Bug fix for SrpV3AxiLite's SsiFrameLimiter
  3. Fixed possible namespace conflicts in the RSSI modules
  4. Update RssiCore.vhd FIFO that don't use pause to AxiStreamResize to save resources
  5. Added UserRst to AxiVersion.py
  6. python update for overlapping variables
  7. Update _Dac38J84.py error clear
  8. Add 'saci' to naming of things to avoid name conflicts

python update for overlapping variables
Author: Larry Ruckman [email protected]
Date: Mon May 14 10:42:52 2018 -0700
Pull: #225 (340 additions, 1116 deletions, 6 files changed)
Branch: slaclab/ESCRYODET-116
Jira: https://jira.slac.stanford.edu/issues/ESCRYODET-116

Notes:

Description

python update for overlapping variables
Update _Dac38J84.py error clear

JIRA

ESCRYODET-116

AxiStreamDepacketizer2 Flow Control Bug Fix
Author: Larry Ruckman [email protected]
Date: Wed May 16 20:33:21 2018 -0700
Pull: #227 (442 additions, 533 deletions, 14 files changed)
Branch: slaclab/rssi-dev

Notes:

Description

  1. AxiStreamDepacketizer2 flow control bug fix
  2. Overhauled the RssiCoreTb
  3. Added fifoWrCnt port to AxiStreamFifoV2.vhd
    • Required for applications that have more than 2 FIFO thresholds)
  1. SsiFrameLimiter now checks for double SOF in a frame
  2. Bug fix for SrpV3AxiLite's SsiFrameLimiter
  3. Fixed possible namespace conflicts in the RSSI modules
  4. Update RssiCore.vhd FIFO that don't use pause to AxiStreamResize to save resources
  5. Added UserRst to AxiVersion.py

JIRA

ESCRYODET-133

Add 'saci' to naming of things to avoid name conflicts
Author: Larry Ruckman [email protected]
Date: Wed May 16 21:58:23 2018 -0700
Pull: #229 (28 additions, 28 deletions, 4 files changed)
Branch: slaclab/kpix-dev

Notes:

Description

Generic 'FrontEnd*' module namers were conflicting with module names in another project

This code is probably way out of date and not working anyway, but for now we'll just change the module names to avoid conflicts.

adding Vivado version checking to protocols/jtag/ruckus.tcl
Author: Larry Ruckman [email protected]
Date: Thu May 17 09:54:23 2018 -0700
Pull: #230 (12 additions, 8 deletions, 1 files changed)
Branch: slaclab/jtag-update

Notes:

Description

adding Vivado version checking to protocols/jtag/ruckus.tcl

Update to SRV3AxiLite
Author: Larry Ruckman [email protected]
Date: Thu May 17 09:51:56 2018 -0700
Pull: #231 (1 additions, 1 deletions, 1 files changed)
Branch: slaclab/srp-dev

Notes:

Description

overflow is only necessary if you are using pause for flow control.
I wass intended to be SLAVE_READY_EN_G from PR #227

Update _Dac38J84.py
Author: Larry Ruckman [email protected]
Date: Mon May 14 09:17:48 2018 -0700
Pull: #226 (1 additions, 0 deletions, 1 files changed)
Branch: slaclab/jmdewart-patch-1

Notes:

Description

ClearAlarms - also clear lane loss, lane alarm

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Patch Release

10 May 17:04
@ruck314 ruck314
v1.8.3
0fbaf30
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Pull Requests

  1. #220 - v1.8.3 release candidate
  2. #222 - PGPv3 6.25Gbps Ultrascale support and SFP I2C revamp
  3. #224 - Migrating optical trasceivers to SFF-8472
  4. #223 - JESD Updates
  5. #219 - adding rxPowerDown and txPowerDown to JESD

Pull Request Details

v1.8.3 release candidate
Author: Larry Ruckman [email protected]
Date: Thu May 10 10:01:37 2018 -0700
Pull: #220 (4143 additions, 2007 deletions, 52 files changed)
Branch: slaclab/pre-release

Notes:

Description

  1. adding rxPowerDown and txPowerDown for JESD
  2. PGPv3 6.25Gbps Ultrascale support and SFP I2C revamp
  3. Adding more pipelining to JESD to help meet timing for high speed (12.5Gbps) applications

JIRA

ESCRYODET-117

PGPv3 6.25Gbps Ultrascale support and SFP I2C revamp
Author: Larry Ruckman [email protected]
Date: Wed May 9 11:21:21 2018 -0700
Pull: #222 (2890 additions, 1355 deletions, 36 files changed)
Branch: slaclab/pgp3-dev

Notes:

Description

  1. Adding support for 6.25Gbps for the Ultrascale FPGA fabric (required for ATLAS)
  2. Depreciating SFP/QSFP/CXP module
  3. Replacing this module with a common SFF-8472 module
  4. Adding Ltc4151 python

Details

This update will break existing .XDC timing constraints. The hierarchy path to RXCLKOUT and TXCLKOUT will need to be updated.

Testing

This build has been tested for 6.25Gbps and regression tested for 10.3125Gbps on KCU1500

Migrating optical trasceivers to SFF-8472
Author: Larry Ruckman [email protected]
Date: Mon May 7 17:44:31 2018 -0700
Pull: #224 (840 additions, 1120 deletions, 18 files changed)
Branch: slaclab/SFF-8472

Notes:

Description

  1. Depreciating SFP/QSFP/CXP module
  2. Replacing this module with a common SFF-8472 module
  3. Adding Ltc4151 python

Note

There is still a lot of work that could be done to make all the SFF-8472 variables into human readable variables. We can add this to the module at a later time.

JESD Updates
Author: Larry Ruckman [email protected]
Date: Wed May 9 13:50:50 2018 -0700
Pull: #223 (1039 additions, 495 deletions, 16 files changed)
Branch: slaclab/jesd-dev

Notes:

Description

Adding more pipeline for performance improvements

adding rxPowerDown and txPowerDown to JESD
Author: Larry Ruckman [email protected]
Date: Wed May 2 18:24:13 2018 -0700
Pull: #219 (264 additions, 207 deletions, 8 files changed)
Branch: slaclab/jesd-pwrdn-support

Notes:

Description

adding rxPowerDown and txPowerDown to JESD

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Patch Release

02 May 16:52
@ruck314 ruck314
v1.8.2
b63060d
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Pull Requests

  1. #218 - v1.8.2 release candidate
  2. #217 - minor gtx7 updates
  3. #216 - _Sa56004x.py bit offsets and sizes fix

Pull Request Details

v1.8.2 release candidate
Author: Larry Ruckman [email protected]
Date: Wed May 2 09:49:48 2018 -0700
Pull: #218 (404 additions, 110 deletions, 4 files changed)
Branch: slaclab/pre-release

Notes:

Description

  1. Updates to _Sa56004x.py
  2. Updates to the PGPv3 GTX7

minor gtx7 updates
Author: Larry Ruckman [email protected]
Date: Wed May 2 09:47:41 2018 -0700
Pull: #217 (397 additions, 103 deletions, 3 files changed)
Branch: slaclab/gtx7-dev

Notes:

Description

  1. adding Gtxe2ChannelDummy.vhd
  2. bug fix for Pgp3Gtx7Wrapper.vhd when REFCLK_G=true

_Sa56004x.py bit offsets and sizes fix
Author: Larry Ruckman [email protected]
Date: Thu Apr 26 14:55:17 2018 -0700
Pull: #216 (7 additions, 7 deletions, 1 files changed)
Branch: slaclab/lzts-dev

Notes:

Description

Fixed Sa56004x bit size and offsets according to the specification.

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Patch Release

25 Apr 15:47
@ruck314 ruck314
v1.8.1
58f916e
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Pull Requests

  1. #215 - v1.8.1 release candidate
  2. #213 - Updates to PGPv3
  3. #214 - CPSW requires all WO variables to be 32-bit size and 32-bit aligned
  4. #212 - Overhauling Debouncer from shift reg to counter based

Pull Request Details

v1.8.1 release candidate
Author: Larry Ruckman [email protected]
Date: Wed Apr 25 08:43:21 2018 -0700
Pull: #215 (564 additions, 413 deletions, 34 files changed)
Branch: slaclab/pre-release

Notes:

Description

  1. Debouncer Update (#212)
  2. PGPv3 updates (#213)
  3. CPSW YAML updates (#214)

Updates to PGPv3
Author: Larry Ruckman [email protected]
Date: Wed Apr 25 08:33:41 2018 -0700
Pull: #213 (447 additions, 357 deletions, 23 files changed)
Branch: slaclab/pgpv3-gtx7-dev

Notes:

Description

  1. Updating PGPv3 default AXI-lite slave buses
  2. Adding EN_DRP_G to 7series QPLL wrapper
  3. For PGPv3.GTX7, routing txPreCursor, txPostCursor and txDiffCtrl to top level wrapper
  4. Bug fixes for _Pgp3AxiL.py
  5. Bug fix for loopback not being routed to the PHY layer
  6. Updating the PROM's python elapsed time print outs
  7. For PGPv3.GTX7, txDataRdy bug fix
    -- refer to Figure 3-12 in UG476 (v1.12)
  8. bug fixes for protTxStart and protTxSequence
    -- I have verified the fix in GTX7 and verified GTH Ultrascale still work after these changes

JIRA

ATLASDAQ-2

CPSW requires all WO variables to be 32-bit size and 32-bit aligned
Author: Larry Ruckman [email protected]
Date: Wed Apr 25 08:33:24 2018 -0700
Pull: #214 (79 additions, 33 deletions, 10 files changed)
Branch: slaclab/cpsw-yaml

Notes:

Description

CPSW requires all WO variables to be 32-bit size and 32-bit aligned

Overhauling Debouncer from shift reg to counter based
Author: Larry Ruckman [email protected]
Date: Fri Apr 20 13:43:48 2018 -0700
Pull: #212 (38 additions, 23 deletions, 1 files changed)
Branch: slaclab/lzts-dev

Notes:

Description

Debouncer was changed to use a counter instead of a shift register. This implementation will allow to make a longer filter without using excessive resources. The generics had to be changed therefore existing projects using debouncer will have to be modified. Removed old generics : FILTER_SIZE_G, FILTER_INIT_G. New generics : CLK_PERIOD_G, DEBOUNCE_PERIOD_G.

Assets 2
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Minor Release

19 Apr 16:04
@ruck314 ruck314
v1.8.0
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Minor Release

Pull Requests

  1. #211 - v1.8.0 release candidate
  2. #205 - Some Ethernet Development
  3. #208 - Adding Micron MT28EW BPI PROM support
  4. #209 - SsiPrbsRateGen Update
  5. #207 - In the Ads42lb69Core fixed cross clock domain synchronization
  6. #206 - Reorganizing the AXI source code
  7. #210 - Variable Overlap bug fix in PGPv3

Pull Request Details

v1.8.0 release candidate
Author: Larry Ruckman [email protected]
Date: Thu Apr 19 08:39:28 2018 -0700
Pull: #211 (4842 additions, 1351 deletions, 168 files changed)
Branch: slaclab/pre-release

Notes:

Description

  1. Reorganizing the AXI source code (#206)
  2. In the Ads42lb69Core fixed cross clock domain synchronization (#207)
  3. Adding Micron MT28EW BPI PROM support (#208)
  4. SsiPrbsRateGen Update (#209)
  5. Variable Overlap bug fix in PGPv3 (#210)

Some Ethernet Development
Author: Larry Ruckman [email protected]
Date: Mon Apr 9 10:44:27 2018 -0700
Pull: #205 (3831 additions, 1237 deletions, 69 files changed)
Branch: slaclab/eth-dev

Notes:

Description

  1. bug fix for gtp7/1GbE's Multi-driven net error when lane>1
  2. Adding surf/ethernet/GigEthCore/gtyUltraScale+ source code
  3. Adding surf/ethernet/XauiCore/gtyUltraScale+ source code
  4. Adding Autneg support to surf/ethernet/GigEthCore
  5. Adding GtyUltraScaleQuadPll wrapper
  6. adding ethernet/TenGigEthCore/gtyUltraScale+
  7. adding ethernet/TenGigEthCore/gthUltraScale+

JIRA

ESCORE-341
ESCORE-310
ESCORE-311
ESCORE-340
ESCORE-309
ESCORE-295

Adding Micron MT28EW BPI PROM support
Author: Larry Ruckman [email protected]
Date: Thu Apr 19 08:31:35 2018 -0700
Pull: #208 (821 additions, 2 deletions, 7 files changed)
Branch: slaclab/ESCORE-334
Jira: https://jira.slac.stanford.edu/issues/ESCORE-334

Notes:

Description

Added Micron MT28EW BPI PROM support

JIRA

ESCORE-334

SsiPrbsRateGen Update
Author: Larry Ruckman [email protected]
Date: Thu Apr 19 08:32:15 2018 -0700
Pull: #209 (72 additions, 74 deletions, 2 files changed)
Branch: slaclab/SsiPrbsRateGen

Notes:

Description

  1. Updating VHDL because breaking apart >32-bit SLV into multiple axiSlaveRegister() no longer required
  2. Updating SsiPrbsRateGen.py to rogue v2.8

In the Ads42lb69Core fixed cross clock domain synchronization
Author: Larry Ruckman [email protected]
Date: Tue Apr 10 13:17:50 2018 -0700
Pull: #207 (50 additions, 26 deletions, 2 files changed)
Branch: slaclab/lzts-dev

Notes:

Description

The configuration and ADC data of the Ads42lb69Core are asynchronous. The invert and convert bits of the configuration were used in the ADC data clock domain without synchronization. This could potentially lead to random issues due to metastability. this is the best candidate to cause the issue described in ESLZTS-30.

Reorganizing the AXI source code
Author: Larry Ruckman [email protected]
Date: Thu Apr 19 08:31:12 2018 -0700
Pull: #206 (56 additions, 4 deletions, 84 files changed)
Branch: slaclab/axi-dir-reorg

Notes:

Description

  1. moved packetizer source code from axi/rtl to protocols/packetizer
  2. moved dma source code from axi/rtl to axi/dma
  3. moved bridge source code from axi/rtl to axi/bridge
  4. moved AXI-Lite source code from axi/rtl to axi/axi-lite
  5. moved AXI-stream source code from axi/rtl to axi/axi-stream
  6. moved AXI4/AXI3 source code from axi/rtl to axi/axi-mem

Variable Overlap bug fix in PGPv3
Author: Larry Ruckman [email protected]
Date: Tue Apr 17 19:37:03 2018 -0700
Pull: #210 (12 additions, 8 deletions, 4 files changed)
Branch: slaclab/Pgp3AxiL.py

Notes:

Description

Fixed overlapping bug in python/surf/protocols/pgp/_Pgp3AxiL.py

Assets 2
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