Patch Release

Pull Requests

1. #583 - v2.0.3 release candidate
2. #581 - Axi stream monitoring updates
3. #582 - Updates for epix development (SACI, ssi_printf, AnalogDevices/ad9249)

Pull Request Details

v2.0.3 release candidate

Author:	Larry Ruckman [email protected]
Date:	Wed Jan 15 11:06:06 2020 -0800
Pull:	#583 (497 additions, 218 deletions, 10 files changed)
Branch:	slaclab/pre-release

Notes:

Description

• Updates for epix development (SACI, ssi_printf, AnalogDevices/ad9249) #582
• Axi stream monitoring updates #581

---

Axi stream monitoring updates

Author:	Larry Ruckman [email protected]
Date:	Thu Jan 9 15:58:02 2020 -0800
Pull:	#581 (479 additions, 212 deletions, 6 files changed)
Branch:	slaclab/AxiStreamMonitoring-update

Notes:

Description

• adding FrameSize support to AxiStreamMon
• exposing AXIS_CONFIG_G to register space
• deprecating AxiStreamMonitoring device class
• reorg of register space with respect to channels
  • Easier to view when using large number of AXIS lanes

---

Updates for epix development (SACI, ssi_printf, AnalogDevices/ad9249)

Author:	Larry Ruckman [email protected]
Date:	Fri Jan 10 16:02:06 2020 -0800
Pull:	#582 (18 additions, 6 deletions, 4 files changed)
Branch:	slaclab/epix-dev

Notes:

Description

• Fixing saciClk not present (when SACI_CLK_HALF_PERIOD_C=64)
• help to close timing at higher clock frequency
• Microblaze cannot make 1 byte writes to the AxiDualPortRam anymore.
  • ixing in the ssi_printf by changingXil_Out8 to Xil_Out32.

---

Patch Release

Pull Requests

1. #579 - v2.0.2 release candidate
2. #578 - Idelaye3Wrapper/Odelaye3Wrapper Usage: syntax bug fix
3. #577 - Update LICENSE.txt
4. #576 - Sff8472.py Python Bug Fix
5. #575 - BoxcarIntegrator.vhd: bug fix for writing to RAM
6. #574 - removed space in Ltc2945.py variable name

Pull Request Details

v2.0.2 release candidate

Author:	Larry Ruckman [email protected]
Date:	Tue Jan 7 09:27:49 2020 -0800
Pull:	#579 (11 additions, 11 deletions, 8 files changed)
Branch:	slaclab/pre-release

Notes:

Description

• removed space in Ltc2945.py variable name #574
• BoxcarIntegrator.vhd: bug fix for writing to RAM #575
• Sff8472.py Python Bug Fix #576
• Idelaye3Wrapper/Odelaye3Wrapper Usage: syntax bug fix #578
• Update LICENSE.txt #577

---

Idelaye3Wrapper/Odelaye3Wrapper Usage: syntax bug fix

Author:	Larry Ruckman [email protected]
Date:	Tue Jan 7 09:21:02 2020 -0800
Pull:	#578 (7 additions, 7 deletions, 4 files changed)
Branch:	slaclab/iowrapper-bug-fix

Notes:

Description

• syntax bug fix for all Idelaye3Wrapper/Odelaye3Wrapper used in SURF FW lib

---

Update LICENSE.txt

Author:	Larry Ruckman [email protected]
Date:	Tue Jan 7 09:21:13 2020 -0800
Pull:	#577 (1 additions, 1 deletions, 1 files changed)
Branch:	slaclab/LICENSE-txt-2020

Notes:

Description

• Updating for year 2020

---

Sff8472.py Python Bug Fix

Author:	Larry Ruckman [email protected]
Date:	Thu Dec 19 10:32:55 2019 -0800
Pull:	#576 (1 additions, 1 deletions, 1 files changed)
Branch:	slaclab/Sff8472-python-bug-fix

Notes:

Description

• removed space in RemoteVariable.name

---

BoxcarIntegrator.vhd: bug fix for writing to RAM

Author:	Larry Ruckman [email protected]
Date:	Tue Dec 17 14:39:09 2019 -0800
Pull:	#575 (1 additions, 1 deletions, 1 files changed)
Branch:	slaclab/BoxcarIntegrator-bug-fix

Notes:

Description

• The RAM write enable strobe was previously 1 cycle out of phase of the write data bus
• This change uses the registered value of wea, aaddra and dina

---

removed space in Ltc2945.py variable name

Author:	Larry Ruckman [email protected]
Date:	Tue Dec 17 09:47:05 2019 -0800
Pull:	#574 (1 additions, 1 deletions, 1 files changed)
Branch:	slaclab/Ltc2945

Notes:

Description

• Updating to CamelCase variable name
• Resolves this bug in rogue software:

Rogue/pyrogue version v4.6.0-1-g382ece2c. https://github.com/slaclab/rogue
WARNING:pyrogue.Device.Ltc4151.BoardPwr:Node ADC Input with one or more special characters will cause lookup errors.
WARNING:pyrogue.Device.Ltc4151.BoardPwr:Node ADC Input with one or more special characters will cause lookup errors.
WARNING:pyrogue.Device.Ltc4151.BoardPwr:Node ADC Input with one or more special characters will cause lookup errors.
WARNING:pyrogue.Device.Ltc4151.BoardPwr:Node ADC Input with one or more special characters will cause lookup errors.

---

Patch Release

Pull Requests

1. #573 - v2.0.1 release candidate
2. #566 - Updating or Removing the last of "work." modules and Ultrscale IODELAY wrapper updates
3. #572 - Reverting "bypassing work around for back-to-back ETH frames for EthMacRxImportXgmii.vhd"
4. #568 - protocols/xvc-udp/ruckus.tcl bug fix
5. #565 - AxiSpiMaster: exposing a copy of the shadow memory
6. #571 - XauiReg.vhd Bug fix
7. #570 - bug fix for protocols/xvc-udp/ruckus.tcl
8. #569 - Ignore the Microblaze autogenerated .TCL files from CopyBdCores()

Pull Request Details

v2.0.1 release candidate

Author:	Larry Ruckman [email protected]
Date:	Fri Dec 13 10:41:39 2019 -0800
Pull:	#573 (152 additions, 873 deletions, 17 files changed)
Branch:	slaclab/pre-release

Notes:

Description

• AxiSpiMaster: exposing a copy of the shadow memory #565
• Ignore the Microblaze autogenerated .TCL files from CopyBdCores() #569
• protocols/xvc-udp/ruckus.tcl bug fix #568
• Updating or Removing the last of "work." modules and Ultrscale IODELAY wrapper updates #566
• bug fix for protocols/xvc-udp/ruckus.tcl #570
• XauiReg.vhd Bug fix #571
• Reverting "bypassing work around for back-to-back ETH frames for EthMacRxImportXgmii.vhd" #572

---

Updating or Removing the last of "work." modules and Ultrscale IODELAY wrapper updates

Author:	Larry Ruckman [email protected]
Date:	Thu Dec 5 13:40:42 2019 -0800
Pull:	#566 (33 additions, 779 deletions, 12 files changed)
Branch:	slaclab/remaining-work-lib

Notes:

Description

• updating from work.AxiStreamSim to surf.RogueTcpStreamWrap
• capatizing all the Makefile
• removing vcs_tb.vhd and its obsolete dependences
• updating all IDELAYE3 to surf.Idelaye3Wrapper
• updating all ODELAYE3 to surf.Odelaye3Wrapper
• depreciating obsolete dma_tb.vhd

---

Reverting "bypassing work around for back-to-back ETH frames for EthMacRxImportXgmii.vhd"

Author:	Larry Ruckman [email protected]
Date:	Thu Dec 12 16:14:27 2019 -0800
Pull:	#572 (41 additions, 37 deletions, 1 files changed)
Branch:	slaclab/ESCORE-514-patch5
Jira:	https://jira.slac.stanford.edu/issues/ESCORE-514-patch5

Notes:

Description

• cab0312#diff-796d952a0151e39fce4245e3019d989e
• There a weird "feature" in the 10GbE PHY where it will strip away the intergap characters and make the ETH frame back-to-back. This only happens if the two ETH frames are min. ETH spacing (measured from commercial ETH NIC card). This works around detects the back-to-back condition and inserts a gap that required for the downstream logic.
• However it appears that it is causing more issues than fixes
• This PR bypasses this "work around" and we can re-investigate this "back-to-back" (no gap) issue at a later time

---

protocols/xvc-udp/ruckus.tcl bug fix

Author:	Larry Ruckman [email protected]
Date:	Thu Dec 5 13:36:38 2019 -0800
Pull:	#568 (34 additions, 29 deletions, 1 files changed)
Branch:	slaclab/xvc-udp-ruckus-bug-fix

Notes:

Description

• Adding virtex Ultrascale+ HBM type to if statement

---

AxiSpiMaster: exposing a copy of the shadow memory

Author:	Larry Ruckman [email protected]
Date:	Tue Dec 3 14:08:08 2019 -0800
Pull:	#565 (24 additions, 23 deletions, 1 files changed)
Branch:	slaclab/AxiSpiMaster-update

Notes:

Description

• AxiSpiMaster: exposing a copy of the shadow memory's RAM interface

---

XauiReg.vhd Bug fix

Author:	Larry Ruckman [email protected]
Date:	Wed Dec 11 11:19:33 2019 -0800
Pull:	#571 (17 additions, 5 deletions, 1 files changed)
Branch:	slaclab/ESCORE-515
Jira:	https://jira.slac.stanford.edu/issues/ESCORE-515

Notes:

Description

• adding missing macConfig.dropOnPause and macConfig.pauseThresh mapping
• Bug create here:
  • d9f38fd#diff-c6bce0facb6ff63e577ec6858990b4c5

---

bug fix for protocols/xvc-udp/ruckus.tcl

Author:	Larry Ruckman [email protected]
Date:	Mon Dec 9 11:09:25 2019 -0800
Pull:	#570 (2 additions, 1 deletions, 1 files changed)
Branch:	slaclab/zynquplusRFSOC

Notes:

Description

• Adding the missing zynquplusRFSOC type to if statement

---

Ignore the Microblaze autogenerated .TCL files from CopyBdCores()

Author:	Larry Ruckman [email protected]
Date:	Thu Dec 5 13:36:20 2019 -0800
Pull:	#569 (2 additions, 0 deletions, 1 files changed)
Branch:	slaclab/ignore-bd-tcl

Notes:

Description

• Related to new .TCL output from slaclab/ruckus#130
• .gitignore the .TCL files from CopyBdCores() ([email protected])

---

Major Release

Pull Requests

1. #561 - v2.0.0 release candidate
2. #541 - ESCORE-335: Refactor all VHDL files and ruckus scripts to use surf as a library
3. #543 - Updating the generics for inferred memory declaration
4. #560 - Remaining work lib leftovers
5. #564 - Update Headers
6. #552 - Gearbox and Scrambler: Bit Reversal Generics
7. #556 - VHDL lib bug fix for GigEthLvdsUltraScale.vhd using SaltUltraScaleCore.dcp
8. #554 - MEMORY_TYPE_G fixes
9. #553 - ClkRst.vhd: clock period rounding error bug fix
10. #555 - bug fix for adding protocols/xvc-udp to surf lib
11. #559 - Misc fw lib bug fixes
12. #563 - removing remaining USE_BUILT_IN_G and XIL_DEVICE_G
13. #558 - bug fix for repeated MEMORY_TYPE_G generic in SsiPrbsRx.vhd

Pull Request Details

v2.0.0 release candidate

Author:	Larry Ruckman [email protected]
Date:	Thu Nov 21 14:46:49 2019 -0800
Pull:	#561 (5745 additions, 7351 deletions, 797 files changed)
Branch:	slaclab/pre-release

Notes:

Description

• Refactor all VHDL files and ruckus scripts to use surf as a library #541
  • Which WILL break existing builds when upgrading
• Depreciated the following generics used in FIFOs and BRAMs (which may breaks existing builds when upgrading) #543
  • BRAM_EN_G (use MEMORY_TYPE_G instead)
  • USE_DSP48_G (remove from code when upgrading)
  • ALTERA_SYN_G (use MEMORY_TYPE_G="altera_mf" instead)
  • ALTERA_RAM_G (use MEMORY_TYPE_G="altera_mf" instead)
  • USE_BUILT_IN_G (use MEMORY_TYPE_G="xpm" instead)
  • XIL_DEVICE_G (use MEMORY_TYPE_G="xpm" instead)
• ClkRst.vhd: clock period rounding error bug fix #553
• Gearbox and Scrambler: Bit Reversal Generics #552
• MEMORY_TYPE_G fixes #554
• VHDL lib bug fix for GigEthLvdsUltraScale.vhd using SaltUltraScaleCore.dcp #556
• bug fix for adding protocols/xvc-udp to surf lib #555
• bug fix for repeated MEMORY_TYPE_G generic in SsiPrbsRx.vhd #558
• Misc fw lib bug fixes #559
• Remaining work lib leftovers #560

---

ESCORE-335: Refactor all VHDL files and ruckus scripts to use surf as a library

Author:	Benjamin Reese [email protected]
Date:	Mon Nov 18 14:43:34 2019 -0800
Pull:	#541 (5133 additions, 3497 deletions, 782 files changed)
Branch:	slaclab/vhdl-lib

Notes:

Description

• Refactor SURF from to use a surf library rather than dumping everything in work
• This prevent namespace conflicts that we are starting to see with other firmware libraries

Details

I've written an explainer for how to refactor your code for these changes:
https://github.com/slaclab/surf/wiki/Refactoring-for-VHDL-Libraries

JIRA

https://jira.slac.stanford.edu/browse/ESCORE-169

Related

#335
This is a recreation of #525. I wanted to change the branch name for consistency across all of our libraries.

---

Updating the generics for inferred memory declaration

Author:	Benjamin Reese [email protected]
Date:	Mon Nov 18 15:04:18 2019 -0800
Pull:	#543 (512 additions, 1832 deletions, 124 files changed)
Branch:	slaclab/BRAM_EN_G-to-MEMORY_TYPE_G

Notes:

Description

• All RAM related modules (including FIFOs) now use the MEMORY_TYPE_G generic instead of BRAM_EN_G.
• This will break existing builds
• Adds support to make URAM with inferred RTL (instead of XPM)
• depreciated ALTERA_SYN_G and ALTERA_RAM_G
• depreciated FifoAsyncBuiltIn and FifoSyncBuiltIn
• removed USE_DSP48_G from all FIFOs
• renaming USE_DSP48_G to USE_DSP_G
  

---

Remaining work lib leftovers

Author:	Benjamin Reese [email protected]
Date:	Thu Nov 21 11:45:44 2019 -0800
Pull:	#560 (19 additions, 1409 deletions, 17 files changed)
Branch:	slaclab/remaining-work-lib-leftovers

Notes:

Description

• Resolving the last remaining work lib dependence in SURF
  • SURF should have zero dependence on VHDL work library

---

Update Headers

Author:	Larry Ruckman [email protected]
Date:	Thu Nov 21 14:01:14 2019 -0800
Pull:	#564 (0 additions, 654 deletions, 654 files changed)
Branch:	slaclab/update-header

Notes:

Description

Remove the -- File: line in every VHDL header. It is useless.

---

Gearbox and Scrambler: Bit Reversal Generics

Author:	Larry Ruckman [email protected]
Date:	Mon Nov 18 15:12:22 2019 -0800
Pull:	#552 (112 additions, 35 deletions, 4 files changed)
Branch:	slaclab/Gearbox

Notes:

Description

• Adding inbound/outboard bit reversal generics to the gearbox and Scrambler
  • I found that I was doing this reversal a lot between these types of modules for some of my applications.
  • Example: https://github.com/slaclab/atlas-rd53-fw-lib/blob/v1.0.0/rtl/AuroraRxLane.vhd#L249
• Bug fix for gearbox

---

VHDL lib bug fix for GigEthLvdsUltraScale.vhd using SaltUltraScaleCore.dcp

Author:	Larry Ruckman [email protected]
Date:	Wed Nov 20 09:36:32 2019 -0800
Pull:	#556 (43 additions, 1 deletions, 2 files changed)
Branch:	slaclab/GigEthLvdsUltraScale-vhdl-lib

Notes:

Description

• VHDL lib bug fix for GigEthLvdsUltraScale.vhd using SaltUltraScaleCore.dcp
• adding .vho to .gitignore
  • Prevent accidental revision control of CreateDcpVhoFiles () files, which have unique headers each time you generate it.
  • https://jira.slac.stanford.edu/browse/ESCORE-504

---

MEMORY_TYPE_G fixes

Author:	Larry Ruckman [email protected]
Date:	Tue Nov 19 14:08:41 2019 -0800
Pull:	#554 (6 additions, 11 deletions, 5 files changed)
Branch:	slaclab/memory_type_g-fixes

Notes:

Description

• Bug fixes for the PR #543 merge

---

ClkRst.vhd: clock period rounding error bug fix

Author:	Larry Ruckman [email protected]
Date:	Mon Nov 18 15:12:13 2019 -0800
Pull:	#553 (14 additions, 2 deletions, 1 files changed)
Branch:	slaclab/ESCORE-501
Jira:	https://jira.slac.stanford.edu/issues/ESCORE-501

Notes:

Description

• Before this PR with a simulation of 1 ps time resolution, the refClk320 would have a period of 3.124 ps

   U_refClk320 : entity work.ClkRst
      generic map (
         CLK_PERIOD_G      => 3.125 ns,  -- 320 MHz
         RST_START_DELAY_G => 0 ns,
         RST_HOLD_TIME_G   => 100 us)
      port map (
         clkP => refClk320,
         rst  => usrRst); 

• This PR fixes this issue by having non-50% duty cycle of the clock period instead of rounding error

---

bug fix for adding protocols/xvc-udp to surf lib

Author:	Larry Ruckman [email protected]
Date:	Wed Nov 20 09:38:16 2019 -0800
Pull:	#555 (4 additions, 4 deletions, 2 files changed)
Branch:	slaclab/xvc-udp

Notes:

Description

• bug fix for adding protocols/xvc-udp to surf lib
• Didn't get added during the refactoring process
  • Probably last minute add without running the refactoring script

---

Misc fw lib bug fixes

Author:	Larry Ruckman [email protected]
Date:	Wed Nov 20 15:03:46 2019 -0800
Pull:	#559 (5 additions, 2 deletions, 3 files changed)
Branch:	slaclab/misc-fw-lib-bug-fixes

Notes:

Description

• VHDL FW lib refactoring bug fix
• bug fix for switching from NUMERIC_STD to std_logic_unsigned/std_logic_arith
• updating GigEthGtp7Wrapper.AXIS_CONFIG_G default
  • make it the same as the other ETH modules

---

removing remaining USE_BUILT_IN_G and XIL_DEVICE_G

Author:	Larry Ruckman [email protected]
Date:	Thu Nov 21 12:31:30 2019 -0800
Pull:	#563 (0 additions, 2 deletions, 1 files changed)
Branch:	slaclab/Fifo-USE_BUILT_IN_G

Notes:

Description

• Found 1 last USE_BUILT_IN_G and XIL_DEVICE_G in Fifo.vhd

---

bug fix for repeated MEMORY_TYPE_G generic in SsiPrbsRx.vhd

Author:	Larry Ruckman [email protected]
Date:	Wed Nov 20 11:37:48 2019 -0800
Pull:	#558 (0 additions, 2 deletions, 1 files changed)
Branch:	slaclab/SsiPrbsRx-bug-fix

Notes:

Description

• bug fix for repea...

Minor Release

Pull Requests

1. #551 - v1.12.0 release candidate
2. #537 - adding current autoneg values to RSSI AXI-Lite interface
3. #549 - Add XVC-UDP JTAG Bridge
4. #550 - Adding Idelaye3Wrapper and Odelaye3Wrapper module
5. #536 - Adding AxiStreamCombiner.vhd and AxiStreamSplitter.vhd
6. #540 - adding support for Si5345 boot ROM and added Pca9506.py
7. #526 - Miscellaneous fixes from TACS development
8. #535 - Add AxiLiteMasterProxy Module
9. #524 - Rogue reorg
10. #539 - Adding generic one-shot module
11. #521 - Updates to Inferred FIFOs and JESD Bus Converters
12. #529 - adding mw-master's AxiLiteRingBuffer.py
13. #522 - Remove Xilinx library dependencies from generic modules
14. #538 - bug fix for rssi autoneg
15. #528 - adding PIPELINE generics to SsiInsertSof
16. #530 - PGPv3: Adding user resetTx feature
17. #546 - Update README.md
18. #548 - AxiVersion.py: prevent rogue crash when timeout on buildStamp register transaction
19. #527 - resolving ieee.numeric_std v.s. ieee.std_logic_unsigned conflicts
20. #547 - Updating AxiVersion.UpTime parser
21. #544 - Update JesdTestStreamTx.vhd
22. #520 - reorganization of axi/dma/
23. #519 - Remove USE_DSP48_G generic that was deprecated in SyncTrigRate module

Pull Request Details

v1.12.0 release candidate

Author:	Larry Ruckman [email protected]
Date:	Thu Nov 14 11:29:00 2019 -0800
Pull:	#551 (3531 additions, 1032 deletions, 106 files changed)
Branch:	slaclab/pre-release

Notes:

Description

• Remove USE_DSP48_G generic that was deprecated in SyncTrigRate module #519
• reorganization of axi/dma/ #520
• Remove Xilinx library dependencies from generic modules #522
• resolving ieee.numeric_std v.s. ieee.std_logic_unsigned conflicts #527
• Miscellaneous fixes from TACS development #526
• Updates to Inferred FIFOs and JESD Bus Converters #521
• Rogue reorg #524
• adding mw-master's AxiLiteRingBuffer.py #529
• Adding AxiStreamCombiner.vhd and AxiStreamSplitter.vhd #536
• adding PIPELINE generics to SsiInsertSof #528
• PGPv3: Adding user resetTx feature #530
• adding current autoneg values to RSSI AXI-Lite interface #537
• bug fix for rssi autoneg #538
• adding support for Si5345 boot ROM and added Pca9506.py #540
• Update JesdTestStreamTx.vhd #544
• Adding generic one-shot module #539
• Updating AxiVersion.UpTime parser #547
• AxiVersion.py: prevent rogue crash when timeout on buildStamp register transaction #548
• Add AxiLiteMasterProxy Module #535
• Add XVC-UDP JTAG Bridge #549
• Adding Idelaye3Wrapper and Odelaye3Wrapper module #550
• Update README.md #546

---

adding current autoneg values to RSSI AXI-Lite interface

Author:	Larry Ruckman [email protected]
Date:	Fri Oct 25 09:51:02 2019 -0700
Pull:	#537 (712 additions, 713 deletions, 5 files changed)
Branch:	slaclab/ESCORE-445
Jira:	https://jira.slac.stanford.edu/issues/ESCORE-445

Notes:

Description

• Add current autoneg values to RSSI AXI-Lite interface
• Redo synchronization
  • Previous version used a HUGE amount of LUTRAM for clock synchronization of configuration registers that 99.9% of the time never change.
  • And if changed, it’s a “set and forget” type of configuration.
  • Therefore we can get away with SynchronizerVector instead of SynchronizerFifo.
  • This will help minimize the resource requirements on small FPGAs like Artix-7.

---

Add XVC-UDP JTAG Bridge

Author:	Larry Ruckman [email protected]
Date:	Thu Nov 14 08:27:23 2019 -0800
Pull:	#549 (930 additions, 0 deletions, 29 files changed)
Branch:	slaclab/udp-jtag-bridge

Notes:

Description

This PR adds a UDP bridge for the Xilinx XVC protocol. This used to live in it's own repository at https://github.com/slaclab/xvc-udp-debug-bridge, but it made sense to merge it in to SURF.

Details

I was unfortunately unable to preserve the history from the old repository. Git LFS messes it all up.

JIRA

Related

---

Adding Idelaye3Wrapper and Odelaye3Wrapper module

Author:	Larry Ruckman [email protected]
Date:	Thu Nov 14 10:26:13 2019 -0800
Pull:	#550 (395 additions, 0 deletions, 3 files changed)
Branch:	slaclab/Delaye3PatchFsm

Notes:

Description

• This modules are wraps on the Xilinx ODELAYE3 and IDELAYE3 primitives with a patching layer to resolve "feature" in the Ultrascale silicon
  • https://forums.xilinx.com/t5/Versal-and-UltraScale/IDELAY-ODELAY-Usage/td-p/812362
• The Xilinx generic and port naming convention maintained in this wrapper

---

Adding AxiStreamCombiner.vhd and AxiStreamSplitter.vhd

Author:	Larry Ruckman [email protected]
Date:	Wed Oct 23 16:50:54 2019 -0700
Pull:	#536 (382 additions, 0 deletions, 2 files changed)
Branch:	slaclab/mw-master-Combiner-Splitter

Notes:

Description

• Adding AxiStreamCombiner.vhd and AxiStreamSplitter.vhd

---

adding support for Si5345 boot ROM and added Pca9506.py

Author:	Larry Ruckman [email protected]
Date:	Thu Oct 31 10:00:08 2019 -0700
Pull:	#540 (235 additions, 10 deletions, 4 files changed)
Branch:	slaclab/Si5345-boot-rom

Notes:

Description

• adding support for Si5345 boot ROM
  • Stores the .mem into a BRAM
• adding Si5345 .csv-to-.mem converter script
• adding surf.devices.nxp.Pca9506.py

---

Miscellaneous fixes from TACS development

Author:	Benjamin Reese [email protected]
Date:	Tue Oct 22 13:58:17 2019 -0700
Pull:	#526 (133 additions, 107 deletions, 2 files changed)
Branch:	slaclab/tacs-dev

Notes:

Description

This will merge in some changes made while developing the TACS project.

• GigEthGtp7Wrapper
  • Add a SIMULATION_G generic
  • Allow selection of DIV2 refclk and output GT clocks
• Fix SpiSlave bug that would appear of CPHA_G='1'

Details

The clocking changes to GigEthGtp7Wrapper will break a few instantiations, but the affected projects all belong to me and I will change them as necessary.

---

Add AxiLiteMasterProxy Module

Author:	Larry Ruckman [email protected]
Date:	Tue Nov 12 13:14:27 2019 -0800
Pull:	#535 (166 additions, 0 deletions, 1 files changed)
Branch:	slaclab/mw-master-AxiLiteMasterProxy

Notes:

Description

• adding AxiLiteMasterProxy.vhd

---

Rogue reorg

Author:	Larry Ruckman [email protected]
Date:	Wed Oct 23 13:05:26 2019 -0700
Pull:	#524 (138 additions, 11 deletions, 3 files changed)
Branch:	slaclab/rogue-reorg

Notes:

Updates needed to move to Rogue v4

Description

The _Adc32Rf45 device produces memory overlap due to the pretense of the rawWrite method calls. So, we need to use overlapEn = True in its registers.

---

Adding generic one-shot module

Author:	Larry Ruckman [email protected]
Date:	Thu Nov 7 10:59:24 2019 -0800
Pull:	#539 (138 additions, 0 deletions, 1 files changed)
Branch:	slaclab/ProgOneShot

Notes:

Description

• Similar to SynchronizerOneShot.vhd but does not include Synchronizer and supports programmable pulse width outputs

---

Updates to Inferred FIFOs and JESD Bus Converters

Author:	Larry Ruckman [email protected]
Date:	Tue Oct 22 18:06:10 2019 -0700
Pull:	#521 (72 additions, 58 deletions, 7 files changed)
Branch:	slaclab/ESCORE-484
Jira:	https://jira.slac.stanford.edu/issues/ESCORE-484

Notes:

Description

• optimizing for resources and timing for LUTRAM inferred FIFOs
• updating rdEn from combinatoric output to registered output for JESD bus downconverters
• bug fix in FifoRdFsm.vhd (related to rdIndex pointer)
• adding comments to code to DualPortRam.vhd

---

adding mw-master's AxiLiteRingBuffer.py

Author:	Larry Ruckman [email protected]
Date:	Wed Oct 23 16:50:15 2019 -0700
Pull:	#529 (106 additions, 0 deletions, 2 files changed)
Branch:	slaclab/AxiLiteRingBuffer-py

Notes:

Description

• adding mw-master's AxiLiteRingBuffer.p...

Minor Release

Pull Requests

1. #518 - v1.11.0 release candidate
2. #507 - Caui4 Update: Adding FEC support via harden IP
3. #516 - Update _Lmk04828.py
4. #497 - resolving memory overlaps and incomplete enum issues
5. #496 - AxiStreamMon Overhaul
6. #512 - deprecating JesdSysrefDly.vhd and increasing sysref delay sweep max from 32 to 256 cycles
7. #506 - adding external clock support for Ultrascale GTH GbE and XAUI
8. #509 - Adding transition frame support to AxiStreamBatcherEventBuilder
9. #503 - adding GEN_ASYNC_G generic to Jesd204bRx.vhd and Jesd204bTx.vhd
10. #498 - encoding a "PGPv2b-like" locData/remData into the unused 56-bit skip code payload
11. #511 - adding SYNTH_MODE_G to all JESD bus width converters
12. #502 - adding multiple JesdTx sync support
13. #505 - adding AxiI2cRegMaster select bus
14. #517 - Travis: Python byte-compile for python syntaxing checking
15. #513 - Change FifoAsync -> Fifo with appropriate generics.
16. #504 - Adding common AxiStreamOctal types
17. #495 - pyrogue: array slicing bug fix
18. #510 - Jesd204bTb: fix broken interface
19. #508 - Updated Adc32Rf45 to only be controlled by LMK SYSREF
20. #493 - Typo fix
21. #500 - performance optimization for SyncMinMax.vhd
22. #499 - Resolved i2cRegSlave.sv bug
23. #501 - bug fix for JesdTx.py
24. #494 - Pgp3 gth us+ bug fix

Pull Request Details

v1.11.0 release candidate

Author:	Larry Ruckman [email protected]
Date:	Sun Oct 20 16:28:07 2019 -0700
Pull:	#518 (3062 additions, 3879 deletions, 55 files changed)
Branch:	slaclab/pre-release

Notes:

Description

• Typo fix #493
• Pgp3 gth us+ bug fix #494
• pyrogue: array slicing bug fix #495
• resolving memory overlaps and incomplete enum issues #497
• AxiStreamMon Overhaul #496
• performance optimization for SyncMinMax.vhd #500
• bug fix for JesdTx.py #501
• adding multiple JesdTx sync support #502
• Resolved i2cRegSlave.sv bug #499
• Adding common AxiStreamOctal types #504
• adding AxiI2cRegMaster select bus #505
• Caui4 Update: Adding FEC support via harden IP #507
• adding external clock support for Ultrascale GTH GbE and XAUI #506
• encoding a "PGPv2b-like" locData/remData into the unused 56-bit skip code payload #498
• Updated Adc32Rf45 to only be controlled by LMK SYSREF #508
• Adding transition frame support to AxiStreamBatcherEventBuilder #509
• adding SYNTH_MODE_G to all JESD bus width converters #511
• deprecating JesdSysrefDly.vhd and increasing sysref delay sweep max from 32 to 256 cycles #512
• Jesd204bTb: fix broken interface #510
• Change FifoAsync -> Fifo with appropriate generics. #513
• Update _Lmk04828.py #516
• Travis: Python byte-compile for python syntaxing checking #517

---

Caui4 Update: Adding FEC support via harden IP

Author:	Larry Ruckman [email protected]
Date:	Thu Oct 10 09:57:22 2019 -0700
Pull:	#507 (902 additions, 812 deletions, 5 files changed)
Branch:	slaclab/ESCORE-480
Jira:	https://jira.slac.stanford.edu/issues/ESCORE-480

Notes:

Description

• adding FEC support via harden IP

---

Update _Lmk04828.py

Author:	Larry Ruckman [email protected]
Date:	Fri Oct 18 09:02:39 2019 -0700
Pull:	#516 (751 additions, 921 deletions, 1 files changed)
Branch:	slaclab/LMK-python-update

Notes:

Description

1. Changed description = "LMK Registers" to actual descriptions of the registers
2. Changing the bitOffset to match the register name with a barrel shift of 2
3. Adding Fixed Register sets into the init() function
4. Reorg the register order to match the data sheet (excluding the aliased registers)

Testing

• In my Generic AMC testing, this fixed the issue where doing ReadAll on the LMK SPI would cause the SYSREF to fluctuate (SysRefPeriodMin != SysRefPeriodMax) and lose JesdRx links

---

resolving memory overlaps and incomplete enum issues

Author:	Larry Ruckman [email protected]
Date:	Fri Sep 27 08:22:12 2019 -0700
Pull:	#497 (336 additions, 1244 deletions, 1 files changed)
Branch:	slaclab/ESCORE-380
Jira:	https://jira.slac.stanford.edu/issues/ESCORE-380

Notes:

Description

• resolving memory overlaps and incomplete enum issues

---

AxiStreamMon Overhaul

Author:	Larry Ruckman [email protected]
Date:	Fri Sep 27 13:23:36 2019 -0700
Pull:	#496 (329 additions, 313 deletions, 6 files changed)
Branch:	slaclab/AxiStreamMonAxiL-logic-optimization

Notes:

Description

• Adding frameCnt register
• Replacing the redundant min/max logic with the common SyncMinMax.vhd module
• Using AxiDualPortRam for AXI-Lite address decode
  • Help with making timing when AXIS_NUM_SLOTS_G is large
• For AxiStreamMonAxiL, using AxiDualPortRam as the one module for clock crossing
  • Instead of the many LUTRAM (SynchronizerFifo) in the submodule
  • Note: SynchronizerFifo optimizes away if SynchronizerFifo.COMMON_CLK_G = true
• Implementing the SyncMinMax with DSP48 primitives

---

deprecating JesdSysrefDly.vhd and increasing sysref delay sweep max from 32 to 256 cycles

Author:	Larry Ruckman [email protected]
Date:	Wed Oct 16 14:52:18 2019 -0700
Pull:	#512 (212 additions, 302 deletions, 9 files changed)
Branch:	slaclab/JesdSysrefDly-replacement

Notes:

Description

• Deprecating JesdSysrefDly.vhd and replacing it with base/general/rtl/SlvDelay.vhd
• Increasing sysref delay sweep max from 32 to 256 cycles

---

adding external clock support for Ultrascale GTH GbE and XAUI

Author:	Larry Ruckman [email protected]
Date:	Thu Oct 10 15:21:17 2019 -0700
Pull:	#506 (148 additions, 100 deletions, 4 files changed)
Branch:	slaclab/ultra-gth-eth-ext-clk

Notes:

Description

• adding external clock support for Ultrascale GTH GbE and XAUI

---

Adding transition frame support to AxiStreamBatcherEventBuilder

Author:	Larry Ruckman [email protected]
Date:	Wed Oct 16 08:44:33 2019 -0700
Pull:	#509 (98 additions, 32 deletions, 2 files changed)
Branch:	slaclab/EVENT-BUILD-TRANS-TDEST

Notes:

Description

• Adding transition frame support to AxiStreamBatcherEventBuilder

---

adding GEN_ASYNC_G generic to Jesd204bRx.vhd and Jesd204bTx.vhd

Author:	Larry Ruckman [email protected]
Date:	Sun Oct 20 09:19:23 2019 -0700
Pull:	#503 (73 additions, 28 deletions, 3 files changed)
Branch:	slaclab/ESCRYODET-401
Jira:	https://jira.slac.stanford.edu/issues/ESCRYODET-401

Notes:

Description

• adding GEN_ASYNC_G generic to Jesd204bRx.vhd and Jesd204bTx.vhd

---

encoding a "PGPv2b-like" locData/remData into the unused 56-bit skip code payload

Author:	Larry Ruckman [email protected]
Date:	Thu Oct 10 15:28:20 2019 -0700
Pull:	#498 (77 additions, 18 deletions, 6 files changed)
Branch:	slaclab/ESCORE-397
Jira:	https://jira.slac.stanford.edu/issues/ESCORE-397

Notes:

Description

• encoding a PGPv2b-like locData/remData into the unused 56-bit skip code payload

---

adding SYNTH_MODE_G to all JESD bus width converters

Author:	Larry Ruckman [email protected]
Date:	Wed Oct 16 14:51:57 2019 -0700
Pull:	#511 (50 additions, 36 deletions, 8 files changed)
Branch:	slaclab/JESD-WIDTH-SYNTH_MODE_G

Notes:

Description

• adding SYNTH_MODE_G to all JESD bus width converters

---

adding multiple JesdTx sync support

Author:	Larry Ruckman [email protected]
Date:	Thu Oct 3 09:15:10 2019 -0700
Pull:	#502 (30 additions, 39 deletions, 1 files changed)
Branch:	slaclab/JesdTx-multi-sync

Notes:

Description

• adding multiple JesdTx sync support
  • used for multiple DAC ICs with different SYNCs
• Addresses the issue in JIRA ESCRYODET-401
• This will break existing builds and require them to map each SYNC with respect to each TX JESD lane

---

adding AxiI2cRegMaster select bus

Author:	Larry Ruckman [email protected]
Date:	Wed Oct 9 16:36:03 2019 -0700
Pull:	#505 (11 additions, 4 deletions, 2 files changed)
Branch:	slaclab/AxiI2cRegMaster-select-bus

Notes:

Description

• adding AxiI2cRegMaster select bus
  • used with I2C analog switch expanders

---

Travis: Python byte-compile for python syntaxing checking

Author:	Larry Ruckman [email protected]
Date:	Fri Oct 18 12:17:39 2019 -0700
Pull:	#517 (8 additions, 4 deletions, 3 files changed)
Branch:	slaclab/travis-Byte-compile-Python

Notes:

Description

• Adding python byte-compile to the travis recipe to check for python syntax errors

---

Change FifoAsync -> Fifo with appropriate generics.

Author:	Larry Ruckman [email protected]
Date:	Thu Oct 17 08:11:55 2019 -0700
Pull:	#513 (6 additions, 6 deletions, 6 files changed)
Branch:	slaclab/jesd-cdc-fifo-fix

Notes:

Description

• Will generate FifoAsync under the hood

---

Adding common AxiStreamOctal types

Author:	Larry Ruckma...

Patch Release

Pull Requests

1. #492 - v1.10.1 release candidate
2. #489 - bug fixes for AxiStreamResize.vhd and AxiStreamPkg.vhd
3. #490 - upgrading travis to Ubuntu Bionic (18.04) and adding ghdl syntax checking
4. #491 - Added AxiStreamDmaV2 XPM/URAM support and Caui4GtyIpWrapper.vhd pipeline update
5. #488 - adding Virtex Ultrascale+ HBM support
6. #487 - bug fix for the PROM erase iterable calculation

Pull Request Details

v1.10.1 release candidate

Author:	Larry Ruckman [email protected]
Date:	Wed Sep 25 16:54:22 2019 -0700
Pull:	#492 (991 additions, 155 deletions, 31 files changed)
Branch:	slaclab/pre-release

Notes:

Description

• bug fix for the PROM erase iterable calculation #487
• bug fixes for AxiStreamResize.vhd and AxiStreamPkg.vhd #489
• adding Virtex Ultrascale+ HBM support #488
• added AxiStreamDmaV2 XPM/URAM support and Caui4GtyIpWrapper.vhd pipeline update #491
• upgrading travis to Ubuntu Bionic (18.04) and adding ghdl syntax checking #490

---

bug fixes for AxiStreamResize.vhd and AxiStreamPkg.vhd

Author:	Larry Ruckman [email protected]
Date:	Wed Sep 25 15:52:07 2019 -0700
Pull:	#489 (827 additions, 53 deletions, 4 files changed)
Branch:	slaclab/AxiStreamResize-bug-fix

Notes:

Description

• bug fix for AxiStreamResize.vhd when SLV_BYTES_C=MST_BYTES_C and SLV_USER_C/=MST_USER_C
• bug fix in AxiStreamPkg.getTKeep when axisConfig.TKEEP_MODE_C = TKEEP_COUNT_C
• adding SSI + AxiStreamFifoV2 + EOFE regression testbed

---

upgrading travis to Ubuntu Bionic (18.04) and adding ghdl syntax checking

Author:	Larry Ruckman [email protected]
Date:	Wed Sep 25 16:11:47 2019 -0700
Pull:	#490 (95 additions, 63 deletions, 6 files changed)
Branch:	slaclab/travis-ci-ghdl

Notes:

Description

• upgrading travis to Ubuntu Bionic (18.04) and adding ghdl syntax checking

---

Added AxiStreamDmaV2 XPM/URAM support and Caui4GtyIpWrapper.vhd pipeline update

Author:	Larry Ruckman [email protected]
Date:	Wed Sep 25 16:49:16 2019 -0700
Pull:	#491 (42 additions, 29 deletions, 4 files changed)
Branch:	slaclab/AxiStreamDmaV2Desc-xpm-uram-support

Notes:

Description

• Added AxiStreamDmaV2 XPM/URAM support
  • Typical AxiStreamDmaV2.DESC_AWIDTH_G=12 fits perfectly into 6 URAMs (instead of 24 BRAM36)
• Set the Caui4GtyIpWrapper.TX_FIFO.PIPE_STAGES_G = 1

---

adding Virtex Ultrascale+ HBM support

Author:	Larry Ruckman [email protected]
Date:	Tue Sep 24 11:59:38 2019 -0700
Pull:	#488 (21 additions, 7 deletions, 14 files changed)
Branch:	slaclab/virtexuplusHBM-support

Notes:

Description

• adding Virtex Ultrascale+ HBM support

---

bug fix for the PROM erase iterable calculation

Author:	Larry Ruckman [email protected]
Date:	Mon Sep 23 12:36:05 2019 -0700
Pull:	#487 (6 additions, 3 deletions, 3 files changed)
Branch:	slaclab/prom-erase-bug-fix

Notes:

Description

• bug fix for the PROM erase iterable calculation

---

Minor Release

Pull Requests

1. #486 - v1.10.0 release candidate
2. #485 - PGP-ETH Version Development Updates
3. #451 - major overhaul of FifoAsync and FifoSync
4. #481 - adding PMbus support to FW/SW
5. #472 - SMURF PCIe Dev Updates
6. #482 - Add AxiLiteSequencerRam.vhd
7. #477 - Si5345Lite.py and Ds32Ev400.py Updates
8. #468 - Adding releaseNotes.py
9. #479 - passing the XPM MEMORY_INIT_FILE/MEMORY_INIT_PARAM to the top-level of AxiDualPortRam.vhd
10. #483 - Changes for the new inferred FIFO Implementation
11. #467 - JesdTx: Updated FW to autodetect changes in test mode type
12. #484 - McsReader.py Optimizations
13. #471 - resolved memory overlay in AxiSysMonUltraScale.py
14. #469 - Ssi frame limiter bug fix
15. #475 - Restoring PR#431
16. #474 - Bug fix for the syntax issues in PR# 469
17. #476 - AxiToAxiLite.vhd: bug fix for write path
18. #470 - adding enableCnt reg to AxiStreamDmaV2Desc.vhd
19. #473 - TrueDualPortRam Port B Dout reset init bugfix (applicable in no-change mode and DOB_REG_G=false)
20. #478 - Ultrascale ClinkDataClk Bug Fix

Pull Request Details

v1.10.0 release candidate

Author:	Larry Ruckman [email protected]
Date:	Mon Sep 23 10:05:54 2019 -0700
Pull:	#486 (12327 additions, 1975 deletions, 282 files changed)
Branch:	slaclab/pre-release

Notes:

Description

• Adding releaseNotes.py #468
• adding enableCnt reg to AxiStreamDmaV2Desc.vhd #470
• TrueDualPortRam Port B Dout reset init bugfix (applicable in no-change mode and DOB_REG_G=false) #473
• Ssi frame limiter bug fix #469
• Bug fix for the syntax issues in PR# 469 #474
• major overhaul of FifoAsync and FifoSync #451
• Restoring PR#431 #475
• SMURF PCIe Dev Updates #472
• AxiToAxiLite.vhd: bug fix for write path #476
• resolved memory overlay in AxiSysMonUltraScale.py #471
• Si5345Lite.py and Ds32Ev400.py Updates #477
• Ultrascale ClinkDataClk Bug Fix #478
• passing the XPM MEMORY_INIT_FILE/MEMORY_INIT_PARAM to the top-level of AxiDualPortRam.vhd #479
• Add AxiLiteSequencerRam.vhd #482
• McsReader.py Optimizations #484
• Changes for the new inferred FIFO Implementation #483
• JesdTx: Updated FW to autodetect changes in test mode type #467
• adding PMbus support to FW/SW #481
• PGP-ETH Version Development Updates #485

---

PGP-ETH Version Development Updates

Author:	Larry Ruckman [email protected]
Date:	Mon Sep 23 10:01:15 2019 -0700
Pull:	#485 (6935 additions, 668 deletions, 224 files changed)
Branch:	slaclab/PGP-ETH-DEV

Notes:

Description

• adding source for PGP-ETH protocol
  • https://confluence.slac.stanford.edu/x/pQmODw
• adding 512-bit support to SSI TX/RX PRBS
  • Required for rate testing the 512-bit wide PGP-ETH AXI stream buses
• adding optional TX AXIS EOFE tagging and depreciating errbit to SsiPrbsRx module
  • errbit depreciated because if significantly bottlenecks the AXI stream if any bit error detected because the logic has to loop through all the bits in the AXI stream data bus (potential 512 clock cycles of deadtime)
• adding AxiLiteRamSyncStatusVector.vhd
• adding XPM support to AxiStreamFifoV2
• adding SgmiiDp83867LvdsUltraScale.vhd
• moved base/general/rtl/DS2411Core.vhd -> devices/Maxim/rtl/DS2411Core.vhd
• moved line-code modules from base/general to protocols/line-codes
• misc. code header updating

---

major overhaul of FifoAsync and FifoSync

Author:	Larry Ruckman [email protected]
Date:	Mon Aug 19 11:51:42 2019 -0700
Pull:	#451 (1550 additions, 821 deletions, 14 files changed)
Branch:	slaclab/ESCORE-429
Jira:	https://jira.slac.stanford.edu/issues/ESCORE-429

Notes:

Description

• major overhaul of FifoAsync and FifoSync to implement the FWFT register output into the BRAM REG
• fixed testbed
• some FIFO dir reorg
• Added some of the XPM wrapper FIFOs
  • XPM not used in the Fifo.vhd yet
  • slowly working towards at in a future major release with XPM FIFO support

Background

While working on the "PacketizerV2: REG_EN_G support" #445 for the PCIe-to-PCIe card commications, it was almost impossible to meet timing when running the PackV2 at 250 MHz without the REG_EN_G enabled. This is due to the large route delay time getting out of the BRAM to the fabric logic. It was clear to me after that PR that we should try to implement the FWFT register output into the BRAM REG to get better performance in our inferred FIFOs, help with meeting timing and reduce place/route time.

Regression Testing

Passed the "FifoFwftTb.vhd" and "SsiPrbsTb.vhd" self checking simulation testbeds.

---

adding PMbus support to FW/SW

Author:	Larry Ruckman [email protected]
Date:	Thu Sep 19 13:57:25 2019 -0700
Pull:	#481 (1677 additions, 0 deletions, 10 files changed)
Branch:	slaclab/PM-BUS-DEV

Notes:

Description

• adding PMbus support to FW/SW

---

SMURF PCIe Dev Updates

Author:	Larry Ruckman [email protected]
Date:	Wed Aug 21 18:14:18 2019 -0700
Pull:	#472 (1064 additions, 178 deletions, 21 files changed)
Branch:	slaclab/UdpEngineTx-TX_FLOW_CTRL_G

Notes:

Description

• adding TX_FLOW_CTRL_G (default=true)
  • True: Blow off the UDP TX data if link down, False: Backpressure until TX link is up
• This prevents the TX Client from locking up if the remote server is disconnected
  • Recovery via the COMM_TIMEOUT_G duration
• This new feature is similar to blowing off the DMA data in the PGP TX direction when the link is down
• Adding AxiStreamDmaFifo.vhd
• adding PIPE_STAGES_G to AxiStreamResize
• python bug fixes
• polishing AxiMemTester and adding busy & start reg
• TenGigEthGthUltraScale: register status to help with making timing
• setting AxiStreamDmaV2Write.U_TrackRam.DOB_REG_G=true to help with making timing
• updating EthMacRxImportXgmii.crcInit to register output to help make making timing
• updating EthMacTxImportXgmii.crcInit to register output to help make making timing

---

Add AxiLiteSequencerRam.vhd

Author:	Larry Ruckman [email protected]
Date:	Wed Sep 18 09:10:00 2019 -0700
Pull:	#482 (590 additions, 0 deletions, 2 files changed)
Branch:	slaclab/AxiLiteSequencerRam

Notes:

Description

The slave AXI-Lite interface used to load a sequence of master AXI-Lite transactions. The transactions are stored in address=[1:2**ADDR_WIDTH_G-1]. Writing to Address[0] will start the transaction sequence and the number of transactions to execute. At the end of the sequence (or if a bus error is detected during the sequence) a slave AXI-lite bus response is executed. If there is a bus error, the address/response/data is written into address[0] of the RAM for debugging.

---

Si5345Lite.py and Ds32Ev400.py Updates

Author:	Larry Ruckman [email protected]
Date:	Thu Sep 5 09:29:44 2019 -0700
Pull:	#477 (54 additions, 146 deletions, 2 files changed)
Branch:	slaclab/SI5345-bug-fix

Notes:

Description

• Update to Si5345Lite.py for phase locking after the CVS load
• Ds32Ev400.py with respect to RD53 development

---

Adding releaseNotes.py

Author:	Larry Ruckman [email protected]
Date:	Fri Aug 9 14:31:16 2019 -0700
Pull:	#468 (180 additions, 0 deletions, 1 files changed)
Branch:	slaclab/releaseNotes

Notes:

Description

• adding releaseNotes.py

---

passing the XPM MEMORY_INIT_FILE/MEMORY_INIT_PARAM to the top-level of AxiDualPortRam.vhd

Author:	Larry Ruckman [email protected]
Date:	Thu Sep 5 11:54:09 2019 -0700
Pull:	#479 (58 additions, 46 deletions, 3 files changed)
Branch:	slaclab/AxiDualPortRam-XPM-INIT-FILE

Notes:

Description

• passing the XPM MEMORY_INIT_FILE/MEMORY_INIT_PARAM to the top-level of AxiDualPortRam.vhd

---

Changes for the new inferred FIFO Implementation

Author:	Larry Ruckman [email protected]
Date:	Thu Sep 19 09:42:20 2019 -0700
Pull:	#483 (91 additions, 12 deletions, 4 files changed)
Branch:	slaclab/JESD-RX-DEBUG

Notes:

Description

• updating new inferred FIFO FSM to have the same rd/wr index latency as old inferred FIFO
• Adding back the original FIFO pipeline on the FIFO's read data path

---

JesdTx: Updated FW to autodetect changes in test mode type

Author:	Larry Ruckman [email protected]
Date:	Thu Sep 19 13:57:03 2019 -0700
Pull:	#467 (29 additions, 50 deletions, 5 files changed)
Branch:	slaclab/ESCORE-458
Jira:	https://jira.slac.stanford.edu/issues/ESCORE-458

Notes:

Description

• update FW to autodetect changes in test mode type
  • instead of toggling the depreciating the TestSigEnable register

---

McsReader.py Optimizations

Author:	Larry Ruckman [email protected]
Date:	Wed Sep 18 15:35:38 2019 -0700
Pull:	#484 (29 additions, 28 deletions, 1 files changed)
Branch:	slaclab/McsReader-optimizing

Notes:

Description

• combined line#75 and #76
• changed bytes to hexBytes
  • Removes a potential namespace conflict
• remove one of the file iterators
• removing the dataList and storing the address/data directly into the numpy array

---

resolved memory overlay in Axi...

Minor Update

Pull Requests

1. #466 - v1.9.11 release candidate
2. #464 - SMURF PCIe Development Updates
3. #457 - TenGigEthGthUltraScale+ Upgrade
4. #449 - HPS Development Branch Enhancements
5. #456 - Changed all ETH wrapper AXIS default ot EMAC_AXIS_CONFIG_C
6. #463 - CameraLink Development Updates
7. #462 - Generalizing the init() routine
8. #458 - (XIL_DEVICE_G = "ULTRASCALE_PLUS") bug fix
9. #465 - Update IQ serial/parallel converter

Pull Request Details

v1.9.11 release candidate

Author:	Larry Ruckman [email protected]
Date:	Mon Aug 5 11:36:05 2019 -0700
Pull:	#466 (1531 additions, 710 deletions, 89 files changed)
Branch:	slaclab/pre-release

Notes:

Description

• HPS Development Branch Enhancements #449
• TenGigEthGthUltraScale+ Upgrade #457
• Changed all ETH wrapper AXIS default ot EMAC_AXIS_CONFIG_C #456
• (XIL_DEVICE_G = "ULTRASCALE_PLUS") bug fix #458
• Generalizing the init() routine #462
• Update IQ serial/parallel converter #465
• SMURF PCIe Development Updates #464
• CameraLink Development Updates #463

---

SMURF PCIe Development Updates

Author:	Larry Ruckman [email protected]
Date:	Mon Aug 5 09:36:55 2019 -0700
Pull:	#464 (703 additions, 487 deletions, 61 files changed)
Branch:	slaclab/smurf-pcie-dev

Notes:

Bug Fixes

• flow control bug fix when using multiple servers or multiple clients (major bug fix)
• work around for back-to-back ETH frames (major bug fix)
• updating PAUSE_512BITS_G for 1 GbE (minor bug fix)
• Fixed the EthMacTxPause's CNT_BITS_C calculation: bitSize(8) = 4 != 3 (minor bug fix)
• Fixed the ETH pause in TX direction

New Features

• updating for programmable pause threshold
• polishing and clean up of TenGigEthReg.py, RssiCore.py and AxiStreamMonitoring.py
• adding TrigDly register to SsiPrbsTx module
• optimized XGMII TX for a 64byte min L2 ETH frame

---

TenGigEthGthUltraScale+ Upgrade

Author:	Larry Ruckman [email protected]
Date:	Fri Jul 19 09:14:54 2019 -0700
Pull:	#457 (602 additions, 71 deletions, 7 files changed)
Branch:	slaclab/TenGigEthGthUltraScale-upgrade

Notes:

Description

• Fixed TenGigEthGthUltraScale+
• Tested and confirmed to work on ZCU102 platform

---

HPS Development Branch Enhancements

Author:	Benjamin Reese [email protected]
Date:	Wed Jul 10 08:59:35 2019 -0700
Pull:	#449 (122 additions, 63 deletions, 6 files changed)
Branch:	slaclab/hps-dev

Notes:

Description

A handful of small enhancements were made in the hps-dev project branch that can now be merged back into the mainline.

• SyncTrigRate now has an option to count trigger edges, not just trigger high time.
• The MEM_ADDR_MASK_G generic of AxiMicronP30 is now readable on and AXI register.
• Pgp2bAxi now counts transitions on RxRemLinkReady.
• Pgp2bGtp7FixedLatency now allows the PGP core to reset the RX PHY.
• The ClkRst simulation clock generator now has a hold input to pause the clock.

---

Changed all ETH wrapper AXIS default ot EMAC_AXIS_CONFIG_C

Author:	Larry Ruckman [email protected]
Date:	Fri Jul 19 09:15:23 2019 -0700
Pull:	#456 (33 additions, 33 deletions, 33 files changed)
Branch:	slaclab/ESCORE-437
Jira:	https://jira.slac.stanford.edu/issues/ESCORE-437

Notes:

Description

• Changed all ETH wrapper AXIS default ot EMAC_AXIS_CONFIG_C
• Matches to the UdpWrapper AXIS configuration

---

CameraLink Development Updates

Author:	Larry Ruckman [email protected]
Date:	Mon Aug 5 11:31:38 2019 -0700
Pull:	#463 (30 additions, 27 deletions, 12 files changed)
Branch:	slaclab/clink-dev

Notes:

Description

• Updating all the "softReset" to "initialize" (starting from rogue v3.5.0)
• fixing Opal1000 naming typo
• bug fix for ClinkChannel resets

---

Generalizing the init() routine

Author:	Larry Ruckman [email protected]
Date:	Thu Aug 1 11:28:39 2019 -0700
Pull:	#462 (15 additions, 15 deletions, 1 files changed)
Branch:	slaclab/Dac38J84-init-update

Notes:

Description

• Generalizing the init() routine

---

(XIL_DEVICE_G = "ULTRASCALE_PLUS") bug fix

Author:	Larry Ruckman [email protected]
Date:	Fri Jul 19 09:17:02 2019 -0700
Pull:	#458 (20 additions, 8 deletions, 4 files changed)
Branch:	slaclab/Iprog-bug-fix

Notes:

Description

• Iprog: (XIL_DEVICE_G = "ULTRASCALE_PLUS") bug fix
• ClkOutBufDiff: (XIL_DEVICE_G = "ULTRASCALE_PLUS") bug fix
• ClkOutBufSingle: (XIL_DEVICE_G = "ULTRASCALE_PLUS") bug fix
• DeviceDna: (XIL_DEVICE_G = "ULTRASCALE_PLUS") bug fix

---

Update IQ serial/parallel converter

Author:	Larry Ruckman [email protected]
Date:	Thu Aug 1 11:34:38 2019 -0700
Pull:	#465 (6 additions, 6 deletions, 2 files changed)
Branch:	slaclab/iq-serial-parallel-update

Notes:

Description

• Update IQ serial/parallel converter

---

Minor Update

Pull Requests

1. #453 - v1.9.10 release candidate
2. #435 - RSSI Development Updates
3. #426 - Adding Ultrascale+ support for PGPv3 and PGPv2b
4. #445 - PacketizerV2: REG_EN_G support
5. #444 - Rxtx polarity ruckman
6. #425 - TenGigEthGtyUltraScale Upgrade and Bug Fix
7. #418 - AxiSpiMaster bug fix for SHADOW_EN_G=true
8. #434 - AxiStreamDmaV2: enforcing 128b descriptor
9. #439 - Revert "Rx/Tx-polarity inputs (optional) added for GigEthCore wrappers"
10. #430 - Rx/Tx-polarity inputs (optional) added for GigEthCore wrappers
11. #432 - Add RFSoC RF data converter PyRogue
12. #452 - Add IQ stream serial/parallel converters - iq32bTo16b and iq16bTo32b
13. #420 - Bug fix for ETH RX Fragment SOF set
14. #443 - bug fix to make DeviceDnaUltraScale agree with JTAG value
15. #421 - Add AxiSysMonUltraScale OT configuration.
16. #437 - Zynq GTP vs. GTX
17. #419 - AxiSpiMaster.vhd: Making AXI-Lite reads to have higher priority than AXI-Lite writes
18. #422 - adding zynquplusRFSOC support
19. #448 - Add axiRdDetect procedure
20. #446 - AxiSysMonUltraScale Updates
21. #429 - BUG: Axi stream mux test bed referred to non existent generics and si…
22. #450 - weByte bug fix for AxiDualPortRam.GEN_INFERRED.AXI_RW_SYS_RW
23. #447 - Gtp7QuadPLL: set BGRCALOVRD to "11111" as per UG482 v1.9, pp. 36
24. #438 - AxiStreamBatcher bug fix
25. #433 - GenericMemoryArray.yaml: fixed merge node
26. #427 - Pgp3GthUsWrapper bug fix
27. #424 - bug fix for LOAD_C_S subtraction
28. #423 - Make sure GitHashShort always displays 7 characters
29. #436 - SsiPrbsTx-bug-fix

Pull Request Details

v1.9.10 release candidate

Author:	Larry Ruckman [email protected]
Date:	Wed Jul 3 15:31:52 2019 -0700
Pull:	#453 (14315 additions, 4149 deletions, 113 files changed)
Branch:	slaclab/pre-release

Notes:

Description

• Zynq GTP vs. GTX #437
• Revert "Rx/Tx-polarity inputs (optional) added for GigEthCore wrappers" #439
• SsiPrbsTx-bug-fix #436
• AxiStreamBatcher bug fix #438
• Rxtx polarity ruckman #444
• bug fix to make DeviceDnaUltraScale agree with JTAG value #443
• Gtp7QuadPLL: set BGRCALOVRD to "11111" as per UG482 v1.9, pp. 36 #447
• AxiSysMonUltraScale Updates #446
• Add axiRdDetect procedure #448
• weByte bug fix for AxiDualPortRam.GEN_INFERRED.AXI_RW_SYS_RW #450
• AxiStreamDmaV2: enforcing 128b descriptor #434
• PacketizerV2: REG_EN_G support #445
• RSSI Development Updates #435
• Add IQ stream serial/parallel converters - iq32bTo16b and iq16bTo32b #452
• AxiSpiMaster bug fix for SHADOW_EN_G=true #418
• AxiSpiMaster.vhd: Making AXI-Lite reads to have higher priority than AXI-Lite writes #419
• Add AxiSysMonUltraScale OT configuration. #421
• Bug fix for ETH RX Fragment SOF set #420
• adding zynquplusRFSOC support #422
• Make sure GitHashShort always displays 7 characters #423
• TenGigEthGtyUltraScale Upgrade and Bug Fix #425
• Adding Ultrascale+ support for PGPv3 and PGPv2b #426
• bug fix for LOAD_C_S subtraction #424
• Pgp3GthUsWrapper bug fix #427
• BUG: Axi stream mux test bed referred to non existent generics and si… #429
• GenericMemoryArray.yaml: fixed merge node #433
• Add RFSoC RF data converter PyRogue #432
• Rx/Tx-polarity inputs (optional) added for GigEthCore wrappers #430

---

RSSI Development Updates

Author:	Larry Ruckman [email protected]
Date:	Wed Jul 3 13:21:19 2019 -0700
Pull:	#435 (4048 additions, 3686 deletions, 32 files changed)
Branch:	slaclab/rssi-interleave-dev

Notes:

Description

• Updating RSSI.ILEAVE_REARB_G to include AxiStreamPacketizer2.PROTO_WORDS_C=3
• Because of ILEAVE_REARB_G value != power of 2, forcing rearb on not(tValid), enforcing ILEAVE_ON_NOTVALID_G=true
• updating CLK_FREQUENCY_G and TIMEOUT_UNIT_G default
• reorg tb and adding RssiInterleaveTb.vhd
• git merge origin/AxiStreamDmaV2-update (#434)
• bug fix for dropped SYN header when remote busy flag asserted
• adding rssiConnected_o port
• adding dynamic ileaveRearb support to AxiStreamMux/RssiWrapper
• bug fix for AxiStreamPacketizer2 and tUserLast value
• optmize for performance
  • preventing the rin output that's connected to the CRC and RAM becoming an output w/ ASYNC reset
• RssiTxFsm flow control bug fix
  • This fixes a bug where the entire frame of the packetizer would get dropped if the packetizer frame's SOF arrives at the same time as (r.buffWe = '1')
• wrapper now autocalculates SEGMENT_ADDR_SIZE_G & MAX_NUM_OUTS_SEG_G
• bug fix: TX/RX window and size should be the same after autoneg
• force MAX_SEG_SIZE_G to be power of 2
• removing busy event generated NULL
  • due to the fact that jittering busy can fill up the TX segment buffer (where NULLs are stored)
• bug fix: prevent changing rxParamam on drops
• fixed bug where the TX checksum would be wrong if busy asserted

---

Adding Ultrascale+ support for PGPv3 and PGPv2b

Author:	Larry Ruckman [email protected]
Date:	Thu Apr 25 12:30:00 2019 -0700
Pull:	#426 (7578 additions, 78 deletions, 21 files changed)
Branch:	slaclab/pgp3-ultrascale_plus

Notes:

Description

• Adding Ultrascale+ support for PGPv3 and PGPv2b

---

PacketizerV2: REG_EN_G support

Author:	Larry Ruckman [email protected]
Date:	Wed Jul 3 13:20:41 2019 -0700
Pull:	#445 (454 additions, 508 deletions, 9 files changed)
Branch:	slaclab/Packetizer2-update

Notes:

Description

• adding REG_EN_G support to PackV2 to help with meeting timing

Note

• Branched from PR##434 because those DMA updates are required for my testing

---

Rxtx polarity ruckman

Author:	Larry Ruckman [email protected]
Date:	Thu Jun 13 12:18:03 2019 -0700
Pull:	#444 (727 additions, 22 deletions, 22 files changed)
Branch:	slaclab/rxtx_polarity_ruckman

Notes:

Same as PR#440, Previous PR accidentally merged into the master branch (instead of the pre-release).

Description

• Removed DCPs from ordinary git tracking to LFS
• Some XSIM bug fixes

---

TenGigEthGtyUltraScale Upgrade and Bug Fix

Author:	Larry Ruckman [email protected]
Date:	Wed Apr 24 11:28:22 2019 -0700
Pull:	#425 (574 additions, 70 deletions, 5 files changed)
Branch:	slaclab/TenGigEthGtyUltraScale-upgrade

Notes:

Description

• Upgrading TenGigEthGtyUltraScale to Vivado 2018.3
• Bug fixes for the GTY Common QPLL configurations

---

AxiSpiMaster bug fix for SHADOW_EN_G=true

Author:	Larry Ruckman [email protected]
Date:	Tue Apr 16 14:28:52 2019 -0700
Pull:	#418 (304 additions, 318 deletions, 5 files changed)
Branch:	slaclab/AxiSpiMaster-bug-fix

Notes:

Description

• AxiSpiMaster bug fix for SHADOW_EN_G=true
• git merge origin/master

---

AxiStreamDmaV2: enforcing 128b descriptor

Author:	Larry Ruckman [email protected]
Date:	Wed Jul 3 13:19:00 2019 -0700
Pull:	#434 (204 additions, 315 deletions, 5 files changed)
Branch:	slaclab/AxiStreamDmaV2-update

Notes:

Description

• AxiStreamDmaV2: enforcing 128b descriptor

---

Revert "Rx/Tx-polarity inputs (optional) added for GigEthCore wrappers"

Author:	Benjamin Reese [email protected]
Date:	Fri May 31 15:24:11 2019 -0700
Pull:	#439 (125 additions, 246 deletions, 19 files changed)
Branch:	slaclab/revert-430-rxtx_polarity

Notes:

Reverts #430

We'll try this again when @till-s gets the LFS stuff right.

---

Rx/Tx-polarity inputs (optional) added for GigEthCore wrappers

Author:	Larry Ruckman [email protected]
Date:	Thu May 23 17:47:28 2019 -0700
Pull:	#430 (246 additions, 125 deletions, 19 files changed)
Branch:	till-s/rxtx_polarity

Notes:

The Tx/Rx-polarity inputs are required if P/N lines are swapped on a PCB (often done for routing reasons).

Description

The modifications use a new DCP which provides the TxPolarity/RxPolarity inputs and routes them out to the top-level wrapper. The respective inputs are assigned default values of '0' so that they don't have to be connected by the user and render the entity backwards compatible.

Details

The modification has been performed for the gtp7, gtx7, gth7, gthU, gthU+ and gtyU+ transceivers. While I have not been able to test all variants on real hardware I have synthesized the 'xxxWrapper.vhd' entities and verified in the synthesized schematics that the new inputs are connected down to the 'xxxCHANNEL' primitives.

Related

Pull request for corresponding modifications of the DCPs.

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Add RFSoC RF data converter PyRogue

Author:	Larry Ruckman [email protected]
Date:	Thu May 23 10:26:48 2019 -0700
Pull:	#432 (296 additions, 0 deletions, 3 files changed)
Branch:	slaclab/rfsoc

Notes:

Description

Add RF data converter and RF data converter tile PyRogue.

---

Add IQ stream serial/parallel converters - iq32bTo16b and iq16bTo32b

Author:	Larry Ruckman [email protected]
Date:	Wed Jul 3 15:02...