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Minor Release v2.43.0

17 Jun 06:23
@ruck314 ruck314
v2.43.0
b40b1e3
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Minor Release v2.43.0

Pull Requests Since v2.42.0

Enhancement

  1. #1083 - Add support for list variables in LMX2615

Unlabeled

  1. #1082 - Xvc wrapper merge
  2. #1085 - update for ClinkFraming.vhd
  3. #1087 - Allow some Adc32Rf45 parameters to be loaded via yaml
  4. #1081 - Update surf_ci.yml
  5. #1088 - bug fix for PgpXvcWrapper.vhd
  6. #1084 - Update to PgpTxVcFifo.vhd
  7. #1080 - updating microblaze/ruckus.tcl
  8. #1079 - _RfDataConverter.py Bug Fix

Pull Request Details

_RfDataConverter.py Bug Fix
Author: Larry Ruckman [email protected]
Date: Thu May 11 17:17:40 2023 -0700
Pull: #1079 (3 additions, 0 deletions, 1 files changed)
Branch: slaclab/RfDataConverter-update

Notes:

Description

  • bug fix to the RfDataConverter.Init() process

updating microblaze/ruckus.tcl
Author: Larry Ruckman [email protected]
Date: Fri May 19 09:50:54 2023 -0700
Pull: #1080 (2 additions, 1 deletions, 1 files changed)
Branch: slaclab/vivado-2023-1

Notes:

Description

  • Vivado 2023.1 did NOT fix the bug with AXI GPIO and system processor reset IP core blocks
  • This issue started in Vivado 2022.2 release

Update surf_ci.yml
Author: Larry Ruckman [email protected]
Date: Wed Jun 7 14:15:01 2023 -0700
Pull: #1081 (2 additions, 9 deletions, 1 files changed)
Branch: slaclab/ESROGUE-619
Jira: https://jira.slac.stanford.edu/issues/ESROGUE-619

Notes:

Description

  • No longer generating anaconda for pre-release

Xvc wrapper merge
Author: Larry Ruckman [email protected]
Date: Tue Jun 13 14:00:48 2023 -0700
Pull: #1082 (270 additions, 5 deletions, 6 files changed)
Branch: slaclab/xvc-wrapper

Notes:

XVC Wrapper is supposed to ease deployment of the XVC-over-PGP.

Add support for list variables in LMX2615
Author: Larry Ruckman [email protected]
Date: Tue Jun 13 09:21:30 2023 -0700
Pull: #1083 (38 additions, 4 deletions, 1 files changed)
Branch: slaclab/rogue_v6
Labels: enhancement

Notes:

This is the one device which did not avoid using rawWrite with Rogue versions past 5.4.

Update to PgpTxVcFifo.vhd
Author: Larry Ruckman [email protected]
Date: Tue Jun 13 08:57:27 2023 -0700
Pull: #1084 (3 additions, 0 deletions, 1 files changed)
Branch: slaclab/PgpTxVcFifo

Notes:

Description

  • adding support for CASCADE_SIZE_G

update for ClinkFraming.vhd
Author: Larry Ruckman [email protected]
Date: Tue Jun 13 12:40:39 2023 -0700
Pull: #1085 (33 additions, 2 deletions, 1 files changed)
Branch: slaclab/clink-deca-mode

Notes:

Description

  • No ZERO padding for DECA mode

Allow some Adc32Rf45 parameters to be loaded via yaml
Author: Benjamin Reese [email protected]
Date: Fri Jun 16 15:30:07 2023 -0700
Pull: #1087 (18 additions, 6 deletions, 2 files changed)
Branch: slaclab/512fft-tkid2

Notes:

Description

Previously, the DDC parameters were hard coded and written during the init routine.
Now they are given default values and allowed to be overridden by a yaml file.

bug fix for PgpXvcWrapper.vhd
Author: Larry Ruckman [email protected]
Date: Fri Jun 16 13:27:52 2023 -0700
Pull: #1088 (1 additions, 2 deletions, 1 files changed)
Branch: slaclab/xvc-wrapper-patch

Notes:

Description

  • Removed output port that doesn't exists
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Minor Release v2.42.0

24 Apr 19:39
@ruck314 ruck314
v2.42.0
c52c352
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Minor Release v2.42.0

Pull Requests Since v2.41.0

Unlabeled

  1. #1061 - Add Rogue Devices for Xilinx GTYE4 DRP Registers
  2. #1068 - adding more RST_ASYNC_G support
  3. #1072 - Adding VHDL Regression Testing to CI workflow
  4. #1074 - Delete AxiStreamFifo.vhd
  5. #1075 - Ruckus tcl fix
  6. #1071 - Delete releaseNotes.py
  7. #1073 - AxiLiteCrossbarI2cMux.vhd update

Pull Request Details

Add Rogue Devices for Xilinx GTYE4 DRP Registers
Author: Benjamin Reese [email protected]
Date: Tue Apr 18 11:22:55 2023 -0700
Pull: #1061 (4761 additions, 0 deletions, 3 files changed)
Branch: slaclab/gtye4-rogue

Notes:

Description

Add Rogue Devices for GTY DRP registers.

adding more RST_ASYNC_G support
Author: Larry Ruckman [email protected]
Date: Mon Apr 24 10:54:02 2023 -0700
Pull: #1068 (1172 additions, 834 deletions, 152 files changed)
Branch: slaclab/ESCORE-782
Jira: https://jira.slac.stanford.edu/issues/ESCORE-782

Notes:

Description

  • Required for ASIC digital designs that are fundamentally ASYNC resets for all FFs

Delete releaseNotes.py
Author: Larry Ruckman [email protected]
Date: Tue Apr 11 07:29:33 2023 -0700
Pull: #1071 (0 additions, 179 deletions, 1 files changed)
Branch: slaclab/ruck314-patch-1

Notes:

Description

Adding VHDL Regression Testing to CI workflow
Author: Larry Ruckman [email protected]
Date: Fri Apr 21 09:34:46 2023 -0700
Pull: #1072 (614 additions, 635 deletions, 182 files changed)
Branch: slaclab/ESCORE-730
Issues: #1072
Jira: https://jira.slac.stanford.edu/issues/ESCORE-730

Notes:

Description

  • Based on cocoTB and GHDL v3.0.0
    • Using standard pytest with code coverage
    • New ruckus + GHDL support to load existing ruckus.tcl scripts
  • Updating ruckus submodule lock to v4.8.0
    • Required for $::env(RUCKUS_PROC_TCL_COMBO) support

GHDL Warning Resolving

During code review, the following should be looked at careful to make sure behavior didn't change:

  • axi/axi-lite/rtl/AxiLitePkg.vhd
  • axi/axi4/rtl/AxiPkg.vhd
  • base/general/rtl/TextUtilPkg.vhd
  • protocols/ssi/rtl/SsiPkg.vhd

AxiLiteCrossbarI2cMux.vhd update
Author: Larry Ruckman [email protected]
Date: Tue Apr 18 10:26:34 2023 -0700
Pull: #1073 (2 additions, 0 deletions, 1 files changed)
Branch: slaclab/AxiLiteCrossbarI2cMux-dev

Notes:

Description

  • adding active HIGH I2C RST output port, which is useful to have in some applications

Delete AxiStreamFifo.vhd
Author: Larry Ruckman [email protected]
Date: Fri Apr 21 13:48:14 2023 -0700
Pull: #1074 (0 additions, 657 deletions, 1 files changed)
Branch: slaclab/AxiStreamFifo-vhd-Depreciating

Notes:

Description

  • Depreciating and deleting AxiStreamFifo.vhd
  • Everyone should be transitioned to AxiStreamFifo.V2vhd at this point

Ruckus tcl fix
Author: Larry Ruckman [email protected]
Date: Mon Apr 24 10:43:33 2023 -0700
Pull: #1075 (170 additions, 170 deletions, 168 files changed)
Branch: slaclab/ruckus-tcl-fix

Notes:

Description

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Minor Release v2.41.0

08 Apr 14:15
@ruck314 ruck314
v2.41.0
db98a64
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Minor Release v2.41.0

Pull Requests Since v2.40.0

Enhancement

  1. #1064 - Fix anaconda build
  2. #1067 - Set min python version to 3.7
  3. #1059 - Remove Python Version Limitation

Unlabeled

  1. #1069 - Removing Legacy Modules
  2. #1062 - adding Init() function to RfDataConverter.py
  3. #1063 - updating .gitignore
  4. #1066 - Fix upload directory
  5. #1060 - AxiPciePhy.py bug fix
  6. #1065 - Fix for conda build

Pull Request Details

Remove Python Version Limitation
Author: Larry Ruckman [email protected]
Date: Tue Apr 4 11:06:25 2023 -0700
Pull: #1059 (1 additions, 1 deletions, 1 files changed)
Branch: slaclab/conda_fix
Labels: enhancement

Notes:

The previous version had python locked to 3.7 which was making it hard to find solutions. This opens up the python verion.

AxiPciePhy.py bug fix
Author: Larry Ruckman [email protected]
Date: Wed Apr 5 09:54:16 2023 -0700
Pull: #1060 (1 additions, 1 deletions, 1 files changed)
Branch: slaclab/AxiPciePhy-bug-fix-16lanes

Notes:

Description

  • Resolve the issue where 16 lanes was reporting zero lanes

adding Init() function to RfDataConverter.py
Author: Larry Ruckman [email protected]
Date: Sat Apr 8 06:59:21 2023 -0700
Pull: #1062 (26 additions, 3 deletions, 1 files changed)
Branch: slaclab/rfdc-init

Notes:

Description

  • Moving this init code that was copy/pasted in multiple root classes into the RFDC device class

updating .gitignore
Author: Larry Ruckman [email protected]
Date: Sat Apr 8 06:59:41 2023 -0700
Pull: #1063 (3 additions, 0 deletions, 1 files changed)
Branch: slaclab/gitignore-update

Notes:

Description

  • ignoring EMACS temp files

Fix anaconda build
Author: Larry Ruckman [email protected]
Date: Thu Apr 6 18:36:14 2023 -0700
Pull: #1064 (11 additions, 6 deletions, 4 files changed)
Branch: slaclab/conda_fix
Labels: enhancement

Notes:

Adds new solver library
Updates meta file structure
Uses pip for python install

This package is now built as a noarch

Fix for conda build
Author: Larry Ruckman [email protected]
Date: Thu Apr 6 19:06:03 2023 -0700
Pull: #1065 (0 additions, 1 deletions, 1 files changed)
Branch: slaclab/conda_fix2

Notes:

Remove Conda Update

Fix upload directory
Author: Larry Ruckman [email protected]
Date: Thu Apr 6 19:20:32 2023 -0700
Pull: #1066 (1 additions, 1 deletions, 1 files changed)
Branch: slaclab/conda_fix2

Notes:

Fix upload source directory.

Set min python version to 3.7
Author: Larry Ruckman [email protected]
Date: Fri Apr 7 10:21:18 2023 -0700
Pull: #1067 (2 additions, 2 deletions, 1 files changed)
Branch: slaclab/min_python
Labels: enhancement

Notes:

This set the min python version to 3.7.

Removing Legacy Modules
Author: Larry Ruckman [email protected]
Date: Sat Apr 8 06:59:57 2023 -0700
Pull: #1069 (0 additions, 735 deletions, 4 files changed)
Branch: slaclab/obsolete-removal

Notes:

Description

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Minor Release v2.40.0

03 Apr 18:14
@ruck314 ruck314
v2.40.0
f771285
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Minor Release v2.40.0

Pull Requests Since v2.39.0

Unlabeled

  1. #1056 - bug fix for AxiLitePkg.vhd to make AxiLiteWrite work for Cadence Genus
  2. #1057 - Sugoi Post-Synthesis Simulation Reset Support

Pull Request Details

bug fix for AxiLitePkg.vhd to make AxiLiteWrite work for Cadence Genus
Author: Larry Ruckman [email protected]
Date: Mon Apr 3 11:08:44 2023 -0700
Pull: #1056 (96 additions, 8 deletions, 1 files changed)
Branch: slaclab/axi-lite-genus-dev

Notes:

Description

  • With the default of constVal = "X", Cadence Genus quietly fails to synthesis the if (constVal /= "X") then statement and optimizes the write data bus away away in synthesis
  • This proposed solution is just add more function overloading for the constVal argument is not used

Sugoi Post-Synthesis Simulation Reset Support
Author: Larry Ruckman [email protected]
Date: Fri Mar 31 10:44:42 2023 -0700
Pull: #1057 (44 additions, 24 deletions, 5 files changed)
Branch: slaclab/sugoi-RST_ASYNC_G

Notes:

Description

  • adding RST_ASYNC_G support to these modules so we can do a ASYNC reset at power up after ASIC post-synthsis.
  • This removes the 'X' signals such that '+vcs+initreg+0' is nolonger required
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Minor Release v2.39.0

28 Mar 22:55
@ruck314 ruck314
v2.39.0
473e1a3
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Minor Release v2.39.0

Pull Requests Since v2.38.1

Unlabeled

  1. #1053 - Updates to xilinx/_RfDataConverter.py
  2. #1055 - Bug fixes _RfBlock.py

Pull Request Details

Updates to xilinx/_RfDataConverter.py
Author: Larry Ruckman [email protected]
Date: Mon Mar 27 15:52:21 2023 -0700
Pull: #1053 (296 additions, 0 deletions, 4 files changed)
Branch: slaclab/rfdc-dev

Notes:

Description

  • Add rfdc support for mixer registers
  • Adding python/surf/xilinx/_RfBlock.py

Bug fixes _RfBlock.py
Author: Larry Ruckman [email protected]
Date: Tue Mar 28 15:49:31 2023 -0700
Pull: #1055 (92 additions, 145 deletions, 3 files changed)
Branch: slaclab/rfdc-dev-bug-fix

Notes:

Description

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Patch Release v2.38.1

21 Mar 18:35
@ruck314 ruck314
v2.38.1
d9db0b5
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Patch Release v2.38.1

Pull Requests Since v2.38.0

Unlabeled

  1. #1051 - Bug fix for AxiStreamDmaRingWrite.vhd
  2. #1046 - Pass PAYLOAD_CNT_TOP_G to Pgp2bTxCell

Pull Request Details

Pass PAYLOAD_CNT_TOP_G to Pgp2bTxCell
Author: Larry Ruckman [email protected]
Date: Tue Mar 21 09:17:23 2023 -0700
Pull: #1046 (2 additions, 1 deletions, 1 files changed)
Branch: slaclab/pgp2b-fix

Notes:

Description

@cbakalis-slac noticed that in Pgp2bTx.vhd, PAYLOAD_CNT_TOP_G was not being passed down into Pgp2bTxCell.

Bug fix for AxiStreamDmaRingWrite.vhd
Author: Larry Ruckman [email protected]
Date: Tue Mar 21 10:37:49 2023 -0700
Pull: #1051 (2 additions, 2 deletions, 1 files changed)
Branch: slaclab/v2.37.2-first-burst-fix

Notes:

Description

  • Fix my bug that wrote the first burst to the wrong address after init.

Contributors

cbakalis-slac
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Patch Release v2.37.2

09 Mar 19:00
@ruck314 ruck314
v2.37.2
6a4c027
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Patch Release v2.37.2

Pull Requests Since v2.37.1

Unlabeled

  1. #1043 - Fix bufferClear mechanism in AxiStreamDmaRingWrite

Pull Request Details

Fix bufferClear mechanism in AxiStreamDmaRingWrite
Author: Larry Ruckman [email protected]
Date: Thu Mar 9 10:37:10 2023 -0800
Pull: #1043 (71 additions, 44 deletions, 1 files changed)
Branch: slaclab/v2.36.0-bufferclear

Notes:

Modify AxiStreamDmaRingWrite module so that the bufferClear input does not corrupt the status or write pointers of other buffers

Fix the bufferClear mechanism in AxiStreamDmaRingWrite.vhd so it no longer corrupts other dma buffers in progress.

Description

The AxiStreamDmaRingWrite module has an input signal bufferClearEn/Addr for clearing any buffer. This feature competes with the state machine that manages the dma address pointers and status for the incoming axisDataMaster. Previously, the bufferClearEn could corrupt both the status and address pointers for one buffer while clearing another. The status update from bufferClearEn is handled promptly, unless a current write to status is underway by the state machine. The address pointer reset from bufferClearEn is cached until the state machine gets to it.

Details

JIRA

Related

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Patch Release v2.37.1

08 Mar 05:37
@ruck314 ruck314
v2.37.1
2763228
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Patch Release v2.37.1

Pull Requests Since v2.37.0

Unlabeled

  1. #1041 - Updating Si5345Lite.py
  2. #1039 - Updates for Cadence Genus Synthesis + Building PGP into an ASIC Support
  3. #1042 - AxiPciePhy.py bug fix
  4. #1036 - Update LICENSE.txt

Pull Request Details

Update LICENSE.txt
Author: Larry Ruckman [email protected]
Date: Thu Feb 16 19:37:50 2023 -0800
Pull: #1036 (1 additions, 1 deletions, 1 files changed)
Branch: slaclab/ruck314-patch-1

Notes:

Description

  • Updating for 2023

Updates for Cadence Genus Synthesis + Building PGP into an ASIC Support
Author: Larry Ruckman [email protected]
Date: Tue Mar 7 09:45:53 2023 -0800
Pull: #1039 (123 additions, 87 deletions, 14 files changed)
Branch: slaclab/cadence-genus

Notes:

Description

Updating Si5345Lite.py
Author: Larry Ruckman [email protected]
Date: Tue Mar 7 21:00:24 2023 -0800
Pull: #1041 (306 additions, 2376 deletions, 2 files changed)
Branch: slaclab/SI5345-dev

Notes:

Description

  • removing overlap variables and using LinkVariables instead

AxiPciePhy.py bug fix
Author: Larry Ruckman [email protected]
Date: Tue Mar 7 21:27:46 2023 -0800
Pull: #1042 (31 additions, 52 deletions, 1 files changed)
Branch: slaclab/AxiPciePhy

Notes:

Description

  • Fixed the issue where PCIe GEN4, GEN5 and GEN6 were not displaying LnkStaSpeed and LnkCapSpeed properly
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Minor Release v2.37.0

16 Feb 20:17
@ruck314 ruck314
v2.37.0
f6e51ac
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Minor Release v2.37.0

Pull Requests Since v2.36.0

Bug

  1. #1032 - Fix Version Generation
  2. #1033 - Bug fix for PR #1032

Enhancement

  1. #1027 - _AxiVersion.py update

Unlabeled

  1. #1034 - SsiPrbs TX/RX bug fixes and Whitespace removal
  2. #1031 - Added _Si5326.py
  3. #1022 - Adding Pgp4RxLite and Pgp4CoreLite + Sc18Is602.vhd bug fix
  4. #1024 - Fix Asynchronous Resets found by Vivado DRC
  5. #1028 - Update surf_ci.yml
  6. #1029 - Update setup.py

Pull Request Details

Adding Pgp4RxLite and Pgp4CoreLite + Sc18Is602.vhd bug fix
Author: Larry Ruckman [email protected]
Date: Wed Jan 25 10:56:39 2023 -0800
Pull: #1022 (535 additions, 75 deletions, 11 files changed)
Branch: slaclab/pgp4-rx-lite

Notes:

Description

Fix Asynchronous Resets found by Vivado DRC
Author: Larry Ruckman [email protected]
Date: Wed Feb 15 19:42:10 2023 -0800
Pull: #1024 (31 additions, 10 deletions, 1 files changed)
Branch: slaclab/async-reset-fix

Notes:

Description

There were a couple resets in SrpV3AxiLite that Vivado DRC complained about.

Whenever a reset is created by ORing together signals, the resulting combinatorial signal should be run through a RstSync block. This should be done even if the signals being ORed belong to the same clock domain, as was the case here.

We should probably discuss this a bit. Maybe it's not that big a problem. I wonder how many other instances of this there are in SURF. It seems Vivado DRC still complains despite this change.

_AxiVersion.py update
Author: Larry Ruckman [email protected]
Date: Mon Jan 30 09:55:29 2023 -0800
Pull: #1027 (1 additions, 1 deletions, 1 files changed)
Branch: slaclab/ESCORE-756
Jira: https://jira.slac.stanford.edu/issues/ESCORE-756
Labels: enhancement

Notes:

Description

Update surf_ci.yml
Author: Larry Ruckman [email protected]
Date: Mon Jan 30 09:55:46 2023 -0800
Pull: #1028 (2 additions, 30 deletions, 1 files changed)
Branch: slaclab/macos-removal

Notes:

Description

  • Removing anaconda macos build

Update setup.py
Author: Larry Ruckman [email protected]
Date: Mon Feb 13 16:16:26 2023 -0800
Pull: #1029 (1 additions, 0 deletions, 1 files changed)
Branch: slaclab/ruck314-patch-1

Notes:

Description

Added _Si5326.py
Author: Larry Ruckman [email protected]
Date: Mon Feb 13 19:06:53 2023 -0800
Pull: #1031 (1223 additions, 0 deletions, 2 files changed)
Branch: slaclab/si5326-dev

Notes:

Description

The _Si5326.py file has been added into python/surf/devices/silabs.
The file starts as a copy of _Si5324.py where the missing registers were added (https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/Si5326.pdf)

Fix Version Generation
Author: Larry Ruckman [email protected]
Date: Wed Feb 15 07:16:00 2023 -0800
Pull: #1032 (9 additions, 3 deletions, 1 files changed)
Branch: slaclab/version
Labels: bug

Notes:

Reformat python version field to be compatible with the new version rules.

Bug fix for PR #1032
Author: Larry Ruckman [email protected]
Date: Wed Feb 15 13:57:15 2023 -0800
Pull: #1033 (1 additions, 1 deletions, 1 files changed)
Branch: slaclab/ruck314-patch-1
Labels: bug

Notes:

Description

  • Variable got renamed from ver to pyVer

SsiPrbs TX/RX bug fixes and Whitespace removal
Author: Larry Ruckman [email protected]
Date: Wed Feb 15 16:48:09 2023 -0800
Pull: #1034 (1233 additions, 1221 deletions, 4 files changed)
Branch: slaclab/SSI-PRBS-bug-fix

Notes:

Description

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Minor Release v2.36.0

07 Dec 16:38
@ruck314 ruck314
v2.36.0
53882e4
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Minor Release v2.36.0

Pull Requests Since v2.35.0

Unlabeled

  1. #1021 - CLINK Update and Bug Fix
  2. #1025 - Adding FORCE_WRAP_ALIGN_G to AxiStreamDmaRingWrite & flake8 fixes
  3. #1020 - Vivado 2022.2 is buggy for general microblaze build

Pull Request Details

Vivado 2022.2 is buggy for general microblaze build
Author: Larry Ruckman [email protected]
Date: Mon Nov 21 08:55:54 2022 -0800
Pull: #1020 (4 additions, 1 deletions, 1 files changed)
Branch: slaclab/vivado-2022.2

Notes:

Description

  • Not able to resolve the broken "AXI GPIO" and "Processor Reset" modules
    • Vivado says the IP version needs upgrading but recommends the same version?!?
  • Decided not to support this version of Vivado for general microblaze build and just abort if user tries to build in this particular version

CLINK Update and Bug Fix
Author: Larry Ruckman [email protected]
Date: Mon Nov 21 10:32:48 2022 -0800
Pull: #1021 (258 additions, 11 deletions, 4 files changed)
Branch: slaclab/CLINK-CM-140MCL-UV

Notes:

Description

Adding FORCE_WRAP_ALIGN_G to AxiStreamDmaRingWrite & flake8 fixes
Author: Larry Ruckman [email protected]
Date: Wed Dec 7 08:12:19 2022 -0800
Pull: #1025 (94 additions, 65 deletions, 8 files changed)
Branch: slaclab/v2.32.0-dmaring-wrap

Notes:

Description

  • In the AxiStreamDmaRingWrite module, add a generic to dynamically resize the DMA to end on endAddr.
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