Skip to content

Releases: slaclab/surf

Patch Release v2.6.6

24 Jun 21:10
@ruck314 ruck314
v2.6.6
80bbcf4
This commit was created on GitHub.com and signed with GitHub’s verified signature. The key has expired.
GPG key ID: 4AEE18F83AFDEB23
Expired
Learn about vigilant mode.
Compare
Choose a tag to compare
Patch Release v2.6.6

Pull Requests Since v2.6.5

Unlabeled

  1. #703 - Release Candidate v2.6.6
  2. #702 - More ESCRYODET-671 development Updates

Pull Request Details

More ESCRYODET-671 development Updates
Author: Larry Ruckman [email protected]
Date: Wed Jun 24 13:55:17 2020 -0700
Pull: #702 (10 additions, 0 deletions, 2 files changed)
Branch: slaclab/ESCRYODET-671
Jira: https://jira.slac.stanford.edu/issues/ESCRYODET-671

Notes:

Description

  • Mapping the LMK RESET at address 0x0 in software
  • Displaying the JESD RX elastic buffer in decimal (instead of HEX)

Release Candidate v2.6.6
Author: Larry Ruckman [email protected]
Date: Wed Jun 24 14:05:45 2020 -0700
Pull: #703 (10 additions, 0 deletions, 2 files changed)
Branch: slaclab/pre-release
Issues: #702

Notes:

Description

  • More ESCRYODET-671 development Updates #702
Assets 2
Loading

Patch Release v2.6.5

23 Jun 20:50
@ruck314 ruck314
v2.6.5
94c87dd
This commit was created on GitHub.com and signed with GitHub’s verified signature. The key has expired.
GPG key ID: 4AEE18F83AFDEB23
Expired
Learn about vigilant mode.
Compare
Choose a tag to compare
Patch Release v2.6.5

Pull Requests Since v2.6.4

Unlabeled

  1. #701 - Release Candidate v2.6.5
  2. #700 - Update _Adc32Rf45.py

Pull Request Details

Update _Adc32Rf45.py
Author: Larry Ruckman [email protected]
Date: Tue Jun 23 13:35:24 2020 -0700
Pull: #700 (16 additions, 23 deletions, 1 files changed)
Branch: slaclab/ESCRYODET-671
Jira: https://jira.slac.stanford.edu/issues/ESCRYODET-671

Notes:

Description

  • Moving the Powerup_AnalogConfig() outside of Init()
    • Powerup_AnalogConfig() should be called before ADC.writeBlocks()

Release Candidate v2.6.5
Author: Larry Ruckman [email protected]
Date: Tue Jun 23 13:47:28 2020 -0700
Pull: #701 (16 additions, 23 deletions, 1 files changed)
Branch: slaclab/pre-release
Issues: #700

Notes:

Description

  • Update _Adc32Rf45.py #700
Assets 2
Loading

Patch Release v2.6.4

22 Jun 23:05
@ruck314 ruck314
v2.6.4
18f1946
This commit was created on GitHub.com and signed with GitHub’s verified signature. The key has expired.
GPG key ID: 4AEE18F83AFDEB23
Expired
Learn about vigilant mode.
Compare
Choose a tag to compare
Patch Release v2.6.4

Pull Requests Since v2.6.3

Unlabeled

  1. #699 - Release Candidate v2.6.4
  2. #698 - Update _Lmk048Base.py

Pull Request Details

Update _Lmk048Base.py
Author: Larry Ruckman [email protected]
Date: Mon Jun 22 15:49:03 2020 -0700
Pull: #698 (11 additions, 35 deletions, 1 files changed)
Branch: slaclab/ESCRYODET-671-1
Jira: https://jira.slac.stanford.edu/issues/ESCRYODET-671-1

Notes:

Description

  • Overhauling the LMK.Init() procedure
    • self.LmkReg_0x0144.set(0x74) is a bug and was preventing DCLK[12,10,8,6] from getting synchronized during the SYNC event

Release Candidate v2.6.4
Author: Larry Ruckman [email protected]
Date: Mon Jun 22 16:02:01 2020 -0700
Pull: #699 (11 additions, 35 deletions, 1 files changed)
Branch: slaclab/pre-release
Issues: #698

Notes:

Description

  • Update _Lmk048Base.py #698
Assets 2
Loading

Patch Release v2.6.3

20 Jun 05:10
@ruck314 ruck314
v2.6.3
59185aa
This commit was created on GitHub.com and signed with GitHub’s verified signature. The key has expired.
GPG key ID: 4AEE18F83AFDEB23
Expired
Learn about vigilant mode.
Compare
Choose a tag to compare
Patch Release v2.6.3

Pull Requests Since v2.6.2

Unlabeled

  1. #697 - Release Candidate v2.6.3
  2. #696 - Update _Lmk048Base.py

Pull Request Details

Update _Lmk048Base.py
Author: Larry Ruckman [email protected]
Date: Fri Jun 19 21:53:17 2020 -0700
Pull: #696 (1 additions, 1 deletions, 1 files changed)
Branch: slaclab/ESCRYODET-671
Jira: https://jira.slac.stanford.edu/issues/ESCRYODET-671

Notes:

Description

  • Bug fix when self.sysrefMode != 0x2

Release Candidate v2.6.3
Author: Larry Ruckman [email protected]
Date: Fri Jun 19 22:06:11 2020 -0700
Pull: #697 (1 additions, 1 deletions, 1 files changed)
Branch: slaclab/pre-release
Issues: #696

Notes:

Description

  • Update _Lmk048Base.py #696
Assets 2
Loading

Patch Release v2.6.2

18 Jun 22:52
@ruck314 ruck314
v2.6.2
bc8385c
This commit was created on GitHub.com and signed with GitHub’s verified signature. The key has expired.
GPG key ID: 4AEE18F83AFDEB23
Expired
Learn about vigilant mode.
Compare
Choose a tag to compare
Patch Release v2.6.2

Pull Requests Since v2.6.1

Unlabeled

  1. #695 - Release Candidate v2.6.2
  2. #691 - RssiAxiLiteRegItf.vhd & Code10b12bPkg.vhd Update
  3. #693 - Bug fixes for AxiStreamCombiner.vhd
  4. #694 - Restoring AXI-Lite response for JESD module from v2.6.0 tag
  5. #692 - AxiStreamCombiner & AxiStreamSplitter Updates

Pull Request Details

RssiAxiLiteRegItf.vhd & Code10b12bPkg.vhd Update
Author: Larry Ruckman [email protected]
Date: Thu Jun 18 10:13:17 2020 -0700
Pull: #691 (15 additions, 4 deletions, 2 files changed)
Branch: slaclab/rssi-reg-patch
Issues: #1, #20

Notes:

Description

  • Removed Code10b12bPkg.vhd whitespace
  • Register mapping bug fix to RssiAxiLiteRegItf.vhd
    • bandwidth_i(1)(63 downto 32) should be mapped to 16#1A# (not 16#20#)

AxiStreamCombiner & AxiStreamSplitter Updates
Author: Larry Ruckman [email protected]
Date: Thu Jun 18 11:31:40 2020 -0700
Pull: #692 (6 additions, 1 deletions, 2 files changed)
Branch: slaclab/AxiStreamCombiner-patch

Notes:

Description

  • adding tDest support to AxiStreamSplitter
  • fixed out of bounds bug in AxiStreamCombiner
    • Example: slaves is 8-bytes and master is 24-bytes will have tData > 512-bit tData in the for loop

Bug fixes for AxiStreamCombiner.vhd
Author: Larry Ruckman [email protected]
Date: Thu Jun 18 15:38:39 2020 -0700
Pull: #693 (3 additions, 6 deletions, 1 files changed)
Branch: slaclab/AxiStreamCombiner-sof

Notes:

Description

  • flow control bug fix for SOF
  • EOFE bug fix

Restoring AXI-Lite response for JESD module from v2.6.0 tag
Author: Larry Ruckman [email protected]
Date: Thu Jun 18 15:38:46 2020 -0700
Pull: #694 (4 additions, 4 deletions, 2 files changed)
Branch: slaclab/axil-resp-patch
Issues: #689

Notes:

Description

  • Confirmed that these were not the cause of the issue
    • Related to PR#689

Release Candidate v2.6.2
Author: Larry Ruckman [email protected]
Date: Thu Jun 18 15:49:25 2020 -0700
Pull: #695 (28 additions, 15 deletions, 6 files changed)
Branch: slaclab/pre-release
Issues: #691, #692, #694, #693

Notes:

Bug Fixes

  • RssiAxiLiteRegItf.vhd & Code10b12bPkg.vhd Update #691
  • AxiStreamCombiner & AxiStreamSplitter Updates #692
  • Restoring AXI-Lite response for JESD module from v2.6.0 tag #694
  • Bug fixes for AxiStreamCombiner.vhd #693
Assets 2
Loading

Patch Release v2.6.1

16 Jun 21:49
@ruck314 ruck314
v2.6.1
4584ef7
This commit was created on GitHub.com and signed with GitHub’s verified signature. The key has expired.
GPG key ID: 4AEE18F83AFDEB23
Expired
Learn about vigilant mode.
Compare
Choose a tag to compare
Patch Release v2.6.1

Pull Requests Since v2.6.0

Unlabeled

  1. #690 - Release Candidate v2.6.1
  2. #689 - revering PR#685 and PR#687

Pull Request Details

revering PR#685 and PR#687
Author: Larry Ruckman [email protected]
Date: Tue Jun 16 14:33:00 2020 -0700
Pull: #689 (37 additions, 45 deletions, 7 files changed)
Branch: slaclab/revert-pr685-and-pr687

Notes:

Description

  • We are seeing strange AXI-Lite behavior with [email protected] for these modules
  • We will resolve this issue after patching surf

Release Candidate v2.6.1
Author: Larry Ruckman [email protected]
Date: Tue Jun 16 14:45:04 2020 -0700
Pull: #690 (37 additions, 45 deletions, 7 files changed)
Branch: slaclab/pre-release
Issues: #685, #687, #689

Notes:

Description

  • Reverting PR#685 and PR#687 #689
Assets 2
Loading

Minor Release v2.6.0

15 Jun 20:22
@ruck314 ruck314
v2.6.0
be45f97
This commit was created on GitHub.com and signed with GitHub’s verified signature. The key has expired.
GPG key ID: 4AEE18F83AFDEB23
Expired
Learn about vigilant mode.
Compare
Choose a tag to compare
Minor Release v2.6.0

Pull Requests Since v2.5.1

Unlabeled

  1. #688 - Release Candidate v2.6.0
  2. #681 - SSP Decoders Development Updates
  3. #678 - adding SelectIoRxGearboxAligner
  4. #686 - Delete SaciSlave2.vhd
  5. #687 - connecting the AXI-Lite responses
  6. #680 - Update Code10b12bPkg.vhd
  7. #684 - Add interrupt holdoff to AxiStreamDmaV2Desc
  8. #679 - Update _Dac38J84.py
  9. #685 - Update JesdRxReg.vhd
  10. #683 - Update _ClinkSerialRx.py
  11. #682 - protocols/xvc-udp/ruckus.tcl update

Pull Request Details

adding SelectIoRxGearboxAligner
Author: Larry Ruckman [email protected]
Date: Thu Jun 4 10:06:55 2020 -0700
Pull: #678 (375 additions, 0 deletions, 1 files changed)
Branch: slaclab/auto-gearbox-align

Notes:

Description

  • Adding SelectIoRxGearboxAligner

Update _Dac38J84.py
Author: Larry Ruckman [email protected]
Date: Mon Jun 8 09:53:35 2020 -0700
Pull: #679 (15 additions, 0 deletions, 1 files changed)
Branch: slaclab/ESCRYODET-667
Jira: https://jira.slac.stanford.edu/issues/ESCRYODET-667

Notes:

Description

-- Adding NcoSync() command

Update Code10b12bPkg.vhd
Author: Larry Ruckman [email protected]
Date: Mon Jun 15 10:10:38 2020 -0700
Pull: #680 (28 additions, 7 deletions, 1 files changed)
Branch: slaclab/Code10b12bPkg

Notes:

Description

  • Adding more control symbols constants

SSP Decoders Development Updates
Author: Larry Ruckman [email protected]
Date: Mon Jun 15 12:07:23 2020 -0700
Pull: #681 (1797 additions, 105 deletions, 16 files changed)
Branch: slaclab/ssp-decoders

Notes:

Description

  • Added errorOut to SspDecoders
  • Added dispErrIn to SspDeframer.vhd
  • Added linkOutOfSync to SelectIoRxGearboxAligner for gearbox alignment
  • Added SelectioDeser for 7-series and Ultrascale+
  • Added SspDecoderLane
    • Supports 10b12b, 12b14b and 16b20b decoding

protocols/xvc-udp/ruckus.tcl update
Author: Larry Ruckman [email protected]
Date: Fri Jun 12 16:05:45 2020 -0700
Pull: #682 (0 additions, 2 deletions, 1 files changed)
Branch: slaclab/2020-dev

Notes:

Description

  • cannot add .DCP as global with Vivado 2020.1 DFX or with use IP Integrator + custom RTL modules

Update _ClinkSerialRx.py
Author: Larry Ruckman [email protected]
Date: Tue Jun 9 15:40:44 2020 -0700
Pull: #683 (3 additions, 3 deletions, 1 files changed)
Branch: slaclab/ClinkSerialRx

Notes:

Description

  • Adding method for detecting response by setting _last to None before sending followed by polling for a value of _last.

Add interrupt holdoff to AxiStreamDmaV2Desc
Author: Ryan Herbst [email protected]
Date: Fri Jun 12 14:02:17 2020 -0700
Pull: #684 (16 additions, 3 deletions, 1 files changed)
Branch: slaclab/dma-interrupt-holdoff

Notes:

Description

Added an interrupt holdoff to delay interrupts for a programmable period after interrupts are re-enabled. This prevents high rate interrupts from monopolizing the processor. Requires support in aes-stream-driver for setting holdoff period, typically done via a command-line parameter to the driver.

Update JesdRxReg.vhd
Author: Larry Ruckman [email protected]
Date: Fri Jun 12 16:05:29 2020 -0700
Pull: #685 (4 additions, 4 deletions, 2 files changed)
Branch: slaclab/Jesd-Reg

Notes:

Description

  • Connecting axilWriteResp to axiSlaveWriteResponse()
  • Connecting axilReadResp to axiSlaveReadResponse()

Delete SaciSlave2.vhd
Author: Larry Ruckman [email protected]
Date: Fri Jun 12 16:05:12 2020 -0700
Pull: #686 (0 additions, 166 deletions, 1 files changed)
Branch: slaclab/saci-update

Notes:

Description

  • Removing SaciSlave2 because identical to SaciSlave

connecting the AXI-Lite responses
Author: Larry Ruckman [email protected]
Date: Mon Jun 15 12:08:33 2020 -0700
Pull: #687 (41 additions, 33 deletions, 5 files changed)
Branch: slaclab/rssi-reg

Notes:

Description

  • Connecting axilWriteResp to axiSlaveWriteResponse()
  • Connecting axilReadResp to axiSlaveReadResponse()

Release Candidate v2.6.0
Author: Larry Ruckman [email protected]
Date: Mon Jun 15 13:13:23 2020 -0700
Pull: #688 (2256 additions, 300 deletions, 29 files changed)
Branch: slaclab/pre-release
Issues: #678, #679, #683, #684, #681, #680, #685, #686, #682, #687

Notes:

New Features

  • adding SelectIoRxGearboxAligner #678
  • Update _Dac38J84.py #679
  • Update _ClinkSerialRx.py #683
  • Add interrupt holdoff to AxiStreamDmaV2Desc #684
  • SSP Decoders Development Updates #681
  • Update Code10b12bPkg.vhd #680

Bug Fixes

  • Update JesdRxReg.vhd #685
  • Delete SaciSlave2.vhd #686
  • protocols/xvc-udp/ruckus.tcl update #682
  • connecting the AXI-Lite responses #687
Assets 2
Loading

Patch Release v2.5.1

29 May 20:11
@ruck314 ruck314
v2.5.1
5cbe2c5
This commit was created on GitHub.com and signed with GitHub’s verified signature. The key has expired.
GPG key ID: 4AEE18F83AFDEB23
Expired
Learn about vigilant mode.
Compare
Choose a tag to compare
Patch Release v2.5.1

Pull Requests Since v2.5.0

Unlabeled

  1. #677 - Release Candidate v2.5.1
  2. #674 - Update SlvDelayFifo.vhd
  3. #670 - Ti ADC Pyrogue Verify Cleanup
  4. #676 - Travis CI Upgrade to dist=focal (Ubuntu 20.04)
  5. #675 - Fix SlvDelayFifo Syntax to Allow VCS Compilation
  6. #671 - Si5345Lite.LoadCsvFile() Update
  7. #672 - Fix SspFramer

Pull Request Details

Ti ADC Pyrogue Verify Cleanup
Author: Larry Ruckman [email protected]
Date: Fri May 29 12:37:32 2020 -0700
Pull: #670 (5 additions, 71 deletions, 3 files changed)
Branch: slaclab/ESCORE-561
Jira: https://jira.slac.stanford.edu/issues/ESCORE-561

Notes:

Description

  • python/surf/devices/ti/_Adc16Dx370.py: removed unused verify arg
  • python/surf/devices/ti/_Ads54J60.py: removed verify arg
  • python/surf/devices/ti/_Ads54J60Channel.py: removed verify arg

Si5345Lite.LoadCsvFile() Update
Author: Larry Ruckman [email protected]
Date: Wed May 27 08:27:44 2020 -0700
Pull: #671 (7 additions, 2 deletions, 1 files changed)
Branch: slaclab/Si5345Lite-update

Notes:

Description

  • Added .csv file extension checking to Si5345Lite.LoadCsvFile()

Fix SspFramer
Author: Larry Ruckman [email protected]
Date: Fri May 29 12:37:06 2020 -0700
Pull: #672 (1 additions, 0 deletions, 1 files changed)
Branch: slaclab/fixSspFramer

Notes:

Description

  • if only 1 WORD was sent in a frame, data is lost. Back-pressure on EOF fixes that.

Update SlvDelayFifo.vhd
Author: Larry Ruckman [email protected]
Date: Thu May 28 08:40:24 2020 -0700
Pull: #674 (64 additions, 46 deletions, 1 files changed)
Branch: slaclab/ESCORE-563
Issues: #674
Jira: https://jira.slac.stanford.edu/issues/ESCORE-563

Notes:

Description

  • combined the data/delay FIFOs together
    • more logic efficient and less resources
  • Prevent delay configurations less than min FIFO latency from being used in readoutTime calculation
  • Added error checking of DELAY_BITS_G with respect to min FIFO latency
  • Using = instead of <= for fifoReadoutTime versus r.timeNow because of bug in the r.timeNow roll over case
  • Using combinatorial output (instead of registered output) for the FIFO's read enable to support 100% FIFO write duty cycles
    • Resolve the issue of lossing data if FIFO writes are more 50% for a long period of time
    • Resolve the issue of two back-to-back FIFO writes and holding off until timeNow roll over to recover of the 2nd read being behind in time
  • Added optional inputAFull for possible flow control

Fix SlvDelayFifo Syntax to Allow VCS Compilation
Author: Benjamin Reese [email protected]
Date: Thu May 28 10:34:37 2020 -0700
Pull: #675 (19 additions, 12 deletions, 1 files changed)
Branch: slaclab/SlvDelayFifo-vcs

Notes:

Description

Fix VHDL syntax so that SlvDelayFifo will compile in VCS.

Details

VCS is really pedantic and raised the following errors:

Parsing design file '/u/re/bareese/projects/lcls2-timetool/firmware/submodules/surf/base/general/rtl/SlvDelayFifo.vhd'
Error-[LOADEXPRFNAMENOTSTATIC] Illegal parameter association
/u/re/bareese/projects/lcls2-timetool/firmware/submodules/surf/base/general/rtl/SlvDelayFifo.vhd, 102
RTL
           din(DATA_FIELD_C)   => inputData,
              ^
  The formal part of association element must be a locally static name.
  Please refer to section 6.1 of the VHDL93 LRM for details about locally 
  static name.
Error-[LOADEXPRFNAMENOTSTATIC] Illegal parameter association
/u/re/bareese/projects/lcls2-timetool/firmware/submodules/surf/base/general/rtl/SlvDelayFifo.vhd, 103
RTL
           din(DELAY_FIELD_C)  => r.readoutTime,
              ^
  The formal part of association element must be a locally static name.
  Please refer to section 6.1 of the VHDL93 LRM for details about locally 
  static name.
Error-[LOADEXPRFNAMENOTSTATIC] Illegal parameter association
/u/re/bareese/projects/lcls2-timetool/firmware/submodules/surf/base/general/rtl/SlvDelayFifo.vhd, 107
RTL
           dout(DATA_FIELD_C)  => fifoReadoutData,
               ^
  The formal part of association element must be a locally static name.
  Please refer to section 6.1 of the VHDL93 LRM for details about locally 
  static name.
Error-[LOADEXPRFNAMENOTSTATIC] Illegal parameter association
/u/re/bareese/projects/lcls2-timetool/firmware/submodules/surf/base/general/rtl/SlvDelayFifo.vhd, 108
RTL
           dout(DELAY_FIELD_C) => fifoReadoutTime,
               ^
  The formal part of association element must be a locally static name.
  Please refer to section 6.1 of the VHDL93 LRM for details about locally 
  static name.

JIRA

Related

Travis CI Upgrade to dist=focal (Ubuntu 20.04)
Author: Larry Ruckman [email protected]
Date: Fri May 29 12:37:18 2020 -0700
Pull: #676 (14 additions, 41 deletions, 3 files changed)
Branch: slaclab/travis-focal

Notes:

Description

  • Update to Ubuntu Focal (20.04)
  • Update to apt install of ghdl
    • now part of default package manger for 20.04
  • Delete ghdl-travis-install.sh
  • Resolving python linter error

Release Candidate v2.5.1
Author: Larry Ruckman [email protected]
Date: Fri May 29 13:07:51 2020 -0700
Pull: #677 (98 additions, 160 deletions, 9 files changed)
Branch: slaclab/pre-release
Issues: #671, #674, #675, #670, #672, #676

Notes:

Description

  • Si5345Lite.LoadCsvFile() Update #671
  • Update SlvDelayFifo.vhd #674
  • Fix SlvDelayFifo Syntax to Allow VCS Compilation #675
  • pr.Device verify cleanup #670
  • Fix SspFramer #672
  • Travis CI Upgrade to dist=focal (Ubuntu 20.04) #676
Assets 2
Loading

Minor Release v2.5.0

18 May 18:05
@ruck314 ruck314
v2.5.0
762c432
This commit was created on GitHub.com and signed with GitHub’s verified signature. The key has expired.
GPG key ID: 4AEE18F83AFDEB23
Expired
Learn about vigilant mode.
Compare
Choose a tag to compare
Minor Release v2.5.0

Pull Requests Since v2.4.0

Bug

  1. #661 - SrpV3AxiTb.vhd + bug fix to SrpV3Core.vhd

Unlabeled

  1. #669 - Release Candidate v2.5.0
  2. #663 - Add AXIL-DRP interface for GigE GTX7
  3. #665 - Adding AxiStreamResizeTb.vhd
  4. #662 - Adding pipeline registers to help with timing for dsp/fixed/BoxcarIntegrator.vhd
  5. #666 - Resolving double YAML load issue
  6. #664 - Add register verify for the read/write registers
  7. #667 - Update _Lmk04828.py
  8. #668 - Cache ClinkSerialRx response for reading

Pull Request Details

SrpV3AxiTb.vhd + bug fix to SrpV3Core.vhd
Author: Larry Ruckman [email protected]
Date: Thu Apr 30 16:03:38 2020 -0700
Pull: #661 (471 additions, 27 deletions, 4 files changed)
Branch: slaclab/SrpV3AxiTb
Labels: bug

Notes:

Description

  • Added SrpV3AxiTb.vhd
  • AXI stream resize bug fix for SrpV3Core.vhd
    • bug fix for when external AXIS is not 32-bit wide tData

Adding pipeline registers to help with timing for dsp/fixed/BoxcarIntegrator.vhd
Author: Larry Ruckman [email protected]
Date: Thu May 14 09:03:31 2020 -0700
Pull: #662 (71 additions, 31 deletions, 2 files changed)
Branch: slaclab/boxcarPipeline

Notes:

trying to address timing closure for MPS Central node. Modified BoxCarIntegrator to add register output to memory used and pipeline for processing. It is optional controlled by generic options. It is not tested yet.

Add AXIL-DRP interface for GigE GTX7
Author: Benjamin Reese [email protected]
Date: Fri May 15 22:35:15 2020 -0700
Pull: #663 (1819 additions, 78 deletions, 7 files changed)
Branch: slaclab/gtx7-drp

Notes:

Description

The GigEth GTX7 DCP core was regenerated in slaclab/surf-dcp-targets#2 to add DRP and txdiffctrl ports. This DCP has been copied into SURF. The DRP ports have been attached to an AxiLiteToDrp bridge and the TX drive strength ports brought out to top level ports.

Some minor cleanup was also done on the GigEthReg python Device class.

Details

Add register verify for the read/write registers
Author: Larry Ruckman [email protected]
Date: Wed May 13 08:53:25 2020 -0700
Pull: #664 (15 additions, 1 deletions, 1 files changed)
Branch: slaclab/ESCRYODET-652
Jira: https://jira.slac.stanford.edu/issues/ESCRYODET-652

Notes:

Description

  • Add register verify for the read/write registers to catch broken SPI interfaces

Adding AxiStreamResizeTb.vhd
Author: Larry Ruckman [email protected]
Date: Thu May 14 09:03:08 2020 -0700
Pull: #665 (292 additions, 0 deletions, 1 files changed)
Branch: slaclab/ESCORE-560
Jira: https://jira.slac.stanford.edu/issues/ESCORE-560

Notes:

Resolving double YAML load issue
Author: Larry Ruckman [email protected]
Date: Thu May 14 13:40:59 2020 -0700
Pull: #666 (60 additions, 8 deletions, 4 files changed)
Branch: slaclab/ESCRYODET-567
Jira: https://jira.slac.stanford.edu/issues/ESCRYODET-567

Notes:

Description

  • Update Init() delays in Adc32Rf45, Dac38J84 and Lmk04828

Update _Lmk04828.py
Author: Larry Ruckman [email protected]
Date: Thu May 14 20:31:36 2020 -0700
Pull: #667 (3 additions, 3 deletions, 2 files changed)
Branch: slaclab/ruck314-patch-1

Notes:

Description

  • Bug fix

Cache ClinkSerialRx response for reading
Author: Larry Ruckman [email protected]
Date: Fri May 15 19:45:12 2020 -0700
Pull: #668 (3 additions, 1 deletions, 1 files changed)
Branch: slaclab/clink_serial_read
Issues: #668

Notes:

Description

Modify _ClinkSerialRx.py to cache received response on serial link to allow read result to be retrieved.

Release Candidate v2.5.0
Author: Larry Ruckman [email protected]
Date: Mon May 18 11:02:45 2020 -0700
Pull: #669 (2734 additions, 149 deletions, 21 files changed)
Branch: slaclab/pre-release
Issues: #664, #665, #662, #666, #667, #668, #663, #661

Notes:

Description

  • Add register verify for the read/write registers #664
  • Adding AxiStreamResizeTb.vhd #665
  • Adding pipeline registers to help with timing for dsp/fixed/BoxcarIntegrator.vhd #662
  • Resolving double YAML load issue #666
  • Update _Lmk04828.py #667
  • Cache ClinkSerialRx response for reading #668
  • Add AXIL-DRP interface for GigE GTX7 #663
  • SrpV3AxiTb.vhd + bug fix to SrpV3Core.vhd #661
Assets 2
Loading

v2.4.0

27 Apr 16:25
@ruck314 ruck314
v2.4.0
70bcfcd
This commit was created on GitHub.com and signed with GitHub’s verified signature. The key has expired.
GPG key ID: 4AEE18F83AFDEB23
Expired
Learn about vigilant mode.
Compare
Choose a tag to compare
v2.4.0

Pull Requests Since v2.3.0

Unlabeled

  1. #659 - release candidate v2.4.0
  2. #657 - Adding Lmk04832 and Lmx2615 python class
  3. #654 - Separated the FSM code out of UartAxiLiteMaster.vhd
  4. #655 - Update SrpV3Axi.vhd and AXI_CONFIG_G/AXI_STREAM_CONFIG_G clean up
  5. #653 - adding Defense Grade RFSoC support and some whitespace removal
  6. #658 - AxiLiteSequencerRam Feature Update
  7. #656 - Add ID,BS,OVL serial commands for Opal

Pull Request Details

adding Defense Grade RFSoC support and some whitespace removal
Author: Larry Ruckman [email protected]
Date: Wed Apr 15 20:13:09 2020 -0700
Pull: #653 (100 additions, 87 deletions, 37 files changed)
Branch: slaclab/XQZU28DR

Notes:

Description

  • adding Defense Grade RFSoC support
  • remove whitespace on all .tcl files
  • remove whitespace on all .vhd files

Separated the FSM code out of UartAxiLiteMaster.vhd
Author: Larry Ruckman [email protected]
Date: Wed Apr 22 11:49:26 2020 -0700
Pull: #654 (363 additions, 282 deletions, 2 files changed)
Branch: slaclab/UartAxiLiteMasterFsm

Notes:

  • Useful for cases when you have a byte stream and no UART serialization
    • Example: SpaceWire endpoint

Update SrpV3Axi.vhd and AXI_CONFIG_G/AXI_STREAM_CONFIG_G clean up
Author: Larry Ruckman [email protected]
Date: Wed Apr 22 11:48:43 2020 -0700
Pull: #655 (111 additions, 123 deletions, 69 files changed)
Branch: slaclab/SrpV3Axi-update

Notes:

Description

  • Force the user to define AXI_CONFIG_G and AXI_STREAM_CONFIG_G
    • Instead of accidentally building with defaults
  • Bug fix for non-32b AXI4 transactions in SrpV3Axi
    • assumed a 4-byte AXI stream, which was mismatched to the AXI4 width

Add ID,BS,OVL serial commands for Opal
Author: Larry Ruckman [email protected]
Date: Thu Apr 16 18:18:29 2020 -0700
Pull: #656 (27 additions, 2 deletions, 1 files changed)
Branch: slaclab/UartOpal_commands

Notes:

Add ID,BS,OVL serial commands for Opal

Description

Added ID,BS,OVL serial commands to python/surf/protocols/clink/_UartOpal1000.py

Adding Lmk04832 and Lmx2615 python class
Author: Larry Ruckman [email protected]
Date: Wed Apr 22 11:48:57 2020 -0700
Pull: #657 (1869 additions, 1129 deletions, 5 files changed)
Branch: slaclab/py-ti-dev

Notes:

Description

  • Adding Lmk04832 (which is 99% the same as Lmk04828)
    • Renamed original Lmk04828 to Lmk048Base
    • Inherited Lmk04828 from Lmk048Base + some exclusive registers
    • Inherited Lmk04832 from Lmk048Base + some exclusive registers
  • Adding Lmx2615 class

AxiLiteSequencerRam Feature Update
Author: Larry Ruckman [email protected]
Date: Wed Apr 22 11:49:09 2020 -0700
Pull: #658 (47 additions, 6 deletions, 1 files changed)
Branch: slaclab/ESCORE-471
Jira: https://jira.slac.stanford.edu/issues/ESCORE-471

Notes:

Description

  • adding discrete start input signal and done output to kick off the sequence

release candidate v2.4.0
Author: Larry Ruckman [email protected]
Date: Thu Apr 23 08:25:23 2020 -0700
Pull: #659 (2517 additions, 1629 deletions, 115 files changed)
Branch: slaclab/pre-release
Issues: #653, #656, #655, #657, #658, #654

Notes:

Description

  • adding Defense Grade RFSoC support and some whitespace removal #653
  • Add ID,BS,OVL serial commands for Opal #656
  • Update SrpV3Axi.vhd and AXI_CONFIG_G/AXI_STREAM_CONFIG_G clean up #655
  • Adding Lmk04832 and Lmx2615 python class #657
  • AxiLiteSequencerRam Feature Update #658
  • Separated the FSM code out of UartAxiLiteMaster.vhd #654
Assets 2
Loading