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Minor Release v2.23.0

12 Jul 17:30
@ruck314 ruck314
v2.23.0
f5d3578
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Minor Release v2.23.0

Pull Requests Since v2.22.0

Unlabeled

  1. #879 - Release Candidate v2.23.0
  2. #878 - Major Overhaul of SALT Protocol
  3. #877 - Pgp4TxLiteWrapper.vhd Update

Pull Request Details

Pgp4TxLiteWrapper.vhd Update
Author: Larry Ruckman [email protected]
Date: Thu Jul 8 12:26:52 2021 -0700
Pull: #877 (11 additions, 11 deletions, 1 files changed)
Branch: slaclab/Pgp4TxLite-flow-control

Notes:

Description

  • exposing phyTxReady for ASIC gearbox flow control

Major Overhaul of SALT Protocol
Author: Larry Ruckman [email protected]
Date: Mon Jul 12 10:25:49 2021 -0700
Pull: #878 (1152 additions, 1706 deletions, 33 files changed)
Branch: slaclab/SALT-overhaul

Notes:

Description

  • Finding issues using the 2016.4 SGMII IP cores that were generated at the time
    • Unable to upgrade IP cores to newer version because user interface breaks + too much IDELAY required for meeting a high density (16 channel) application
  • Since 2016, surf now has gearbox modules and SELECTIO aligners such that the SGMII IP core is no longer need
  • In this PR, I remove the .DCP IP cores complete and replace them with surf-based RTL

Release Candidate v2.23.0
Author: Larry Ruckman [email protected]
Date: Mon Jul 12 10:26:03 2021 -0700
Pull: #879 (1163 additions, 1717 deletions, 34 files changed)
Branch: slaclab/pre-release
Issues: #877, #878

Notes:

Description

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Minor Release v2.22.0

07 Jul 23:26
@ruck314 ruck314
v2.22.0
7b09e90
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Minor Release v2.22.0

Pull Requests Since v2.21.0

Unlabeled

  1. #876 - Release Candidate v2.22.0
  2. #875 - adding Pgp4TxLite

Pull Request Details

adding Pgp4TxLite
Author: Larry Ruckman [email protected]
Date: Wed Jul 7 15:57:20 2021 -0700
Pull: #875 (1001 additions, 0 deletions, 6 files changed)
Branch: slaclab/PGPv4-Lite

Notes:

Description

  • Pgp4TxLite does NOT support following
    • AXI stream interleaving
    • SOC/EOC k-words
    • TKEEP for last transfer != 8-byte word (already 64-bit data words)
  • Add generates to optimize for no flow control
  • Add generates to optimize for no SKIP codes
    • Used only when dealing with a clock synchronous system
  • Based on the pgp3-lite development branch that Ben previously worked on
  • Pgp4TxLiteWrapper.vhd design to be a module to drop directly into an ASIC design
    • Similar framing signals as SSP protocol
  • Pgp4TxLite protocol output is design to go directly into existing Pgp4Rx (no changes to RX required)

Release Candidate v2.22.0
Author: Larry Ruckman [email protected]
Date: Wed Jul 7 16:22:01 2021 -0700
Pull: #876 (1001 additions, 0 deletions, 6 files changed)
Branch: slaclab/pre-release
Issues: #875

Notes:

Description

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Minor Release v2.21.0

06 Jul 18:28
@ruck314 ruck314
v2.21.0
85876dd
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Minor Release v2.21.0

Pull Requests Since v2.20.0

Unlabeled

  1. #874 - Release Candidate v2.21.0
  2. #873 - Updates to python/surf/devices/transceivers
  3. #872 - Adding AxiLiteCrossbarI2cMux.vhd

Pull Request Details

Adding AxiLiteCrossbarI2cMux.vhd
Author: Larry Ruckman [email protected]
Date: Tue Jul 6 11:00:59 2021 -0700
Pull: #872 (603 additions, 74 deletions, 4 files changed)
Branch: slaclab/i2c-mux-fsm

Notes:

Description

  • AxiLiteCrossbarI2cMux.vhd sets the I2C multiplexer path before forwarding the transaction to the AXI-Lite crossbar
    • Assumes only I2C modules connected after the AXI-Lite crossbar
    • Support for TCA9548, PCA9547, PCA9544A and PCA9540B
  • Partitioning AxiI2cRegMaster to be a wrapper on AxiI2cRegMasterCore such that multiple AxiI2cRegMaster can share the same I2C bus

Updates to python/surf/devices/transceivers
Author: Larry Ruckman [email protected]
Date: Tue Jul 6 11:01:12 2021 -0700
Pull: #873 (731 additions, 97 deletions, 7 files changed)
Branch: slaclab/qsfp_python

Notes:

Description

  • adding more diagnostic registers to Qsfp.py
  • combined parseStrArray16Byte() & parseStrArray4Byte() into parseStrArrayByte()

Release Candidate v2.21.0
Author: Larry Ruckman [email protected]
Date: Tue Jul 6 11:23:48 2021 -0700
Pull: #874 (731 additions, 97 deletions, 7 files changed)
Branch: slaclab/pre-release
Issues: #872, #873

Notes:

Description

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Minor Release v2.20.0

30 Jun 04:54
@ruck314 ruck314
v2.20.0
aaf901a
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Minor Release v2.20.0

Pull Requests Since v2.19.2

Unlabeled

  1. #871 - Release Candidate v2.20.0
  2. #870 - Sff8472 can't support both SFP/QSFP so breaking it apart per device type
  3. #868 - Renaming PGP-ETH to HTSP
  4. #869 - Exposing PGP rogue sim's EN_SIDEBAND_G to top-level
  5. #867 - DspComparator.vhd Update

Pull Request Details

DspComparator.vhd Update
Author: Larry Ruckman [email protected]
Date: Mon Jun 14 10:13:32 2021 -0700
Pull: #867 (1 additions, 2 deletions, 1 files changed)
Branch: slaclab/DspComparator-update

Notes:

Description

  • DSP slices now support cascading for wider subtractions

Renaming PGP-ETH to HTSP
Author: Larry Ruckman [email protected]
Date: Mon Jun 28 11:19:31 2021 -0700
Pull: #868 (496 additions, 494 deletions, 17 files changed)
Branch: slaclab/HTSP-dev

Notes:

Description

  • Decided to change the name after Dionisio and I started to write the JINST paper
    • Better to change the name now before it gets deployed into the field

Exposing PGP rogue sim's EN_SIDEBAND_G to top-level
Author: Larry Ruckman [email protected]
Date: Tue Jun 29 09:40:57 2021 -0700
Pull: #869 (47 additions, 27 deletions, 10 files changed)
Branch: slaclab/RoguePgpSim-sideband

Notes:

Description

  • Useful to be able to disable that feature if not used in the simulation (not always used)

Sff8472 can't support both SFP/QSFP so breaking it apart per device type
Author: Larry Ruckman [email protected]
Date: Tue Jun 29 21:43:14 2021 -0700
Pull: #870 (582 additions, 591 deletions, 4 files changed)
Branch: slaclab/sfp-i2c-dev

Notes:

Description

  • Update the diagnostics to be more human readable
  • Simplified the default GUI displayed variables
  • Remove the generic _Sff8472.py and replaced it with a _Sfp.py and _Qsfp.py

Release Candidate v2.20.0
Author: Larry Ruckman [email protected]
Date: Tue Jun 29 21:50:10 2021 -0700
Pull: #871 (1126 additions, 1114 deletions, 32 files changed)
Branch: slaclab/pre-release
Issues: #867, #868, #869, #870

Notes:

Description

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Patch Release v2.19.2

07 Jun 22:18
@slacrherbst slacrherbst
v2.19.2
62d17a7
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Patch Release v2.19.2

Pull Requests Since v2.19.1

Unlabeled

  1. #861 - Release Candidate v2.19.2
  2. #801 - Use DualPortRam instead of local inferred RAM for AxiSpiMaster shadow RAM
  3. #864 - Updates to SspLowSpeedDecoders and SelectIoRxGearboxAligner
  4. #865 - adding EXT_QPLL_G generic to Gtpe2ChannelDummy.vhd
  5. #863 - exposing rxoutclk for GTH3, GTH4 and GTY4 dummy terminations modules
  6. #866 - whitespace removal
  7. #862 - Update SimpleDualPortRam.vhd and TrueDualPortRam.vhd
  8. #860 - reverted locked behavior for mmcm simulation

Pull Request Details

Use DualPortRam instead of local inferred RAM for AxiSpiMaster shadow RAM
Author: Benjamin Reese [email protected]
Date: Thu Jun 3 12:43:17 2021 -0700
Pull: #801 (40 additions, 34 deletions, 1 files changed)
Branch: slaclab/axi-spi-shadow-ram

Notes:

Description

The locally inferred RAM would create an enormous mem signal in simulation even if SHADOW_EN_G=false. This change uses a DualPortRam within a generate block instead.

reverted locked behavior for mmcm simulation
Author: Larry Ruckman [email protected]
Date: Fri May 21 14:33:50 2021 -0700
Pull: #860 (1 additions, 1 deletions, 1 files changed)
Branch: slaclab/mmcm_sim_revert

Notes:

Description

  • reverting back due to weird behavior in VCS

Release Candidate v2.19.2
Author: Larry Ruckman [email protected]
Date: Mon Jun 7 15:13:28 2021 -0700
Pull: #861 (146 additions, 119 deletions, 17 files changed)
Branch: slaclab/pre-release
Issues: #860, #862, #863, #864, #865, #866, #801

Notes:

Description

  • reverted locked behavior for mmcm simulation #860
  • Update SimpleDualPortRam.vhd and TrueDualPortRam.vhd #862
  • exposing rxoutclk for GTH3, GTH4 and GTY4 dummy terminations modules #863
  • Updates to SspLowSpeedDecoders and SelectIoRxGearboxAligner #864
  • adding EXT_QPLL_G generic to Gtpe2ChannelDummy.vhd #865
  • whitespace removal #866
  • Use DualPortRam instead of local inferred RAM for AxiSpiMaster shadow RAM #801

Update SimpleDualPortRam.vhd and TrueDualPortRam.vhd
Author: Larry Ruckman [email protected]
Date: Mon May 24 14:30:40 2021 -0700
Pull: #862 (6 additions, 7 deletions, 2 files changed)
Branch: slaclab/SimpleDualPortRam-update

Notes:

Description

  • Initializing the signals such that they are not U at the start of the simulation

exposing rxoutclk for GTH3, GTH4 and GTY4 dummy terminations modules
Author: Larry Ruckman [email protected]
Date: Wed May 26 09:27:41 2021 -0700
Pull: #863 (21 additions, 18 deletions, 3 files changed)
Branch: slaclab/GtDummy-update

Notes:

Description

  • Required if terminating external OBUFDS_GTE

Updates to SspLowSpeedDecoders and SelectIoRxGearboxAligner
Author: Larry Ruckman [email protected]
Date: Wed Jun 2 09:49:29 2021 -0700
Pull: #864 (39 additions, 30 deletions, 5 files changed)
Branch: slaclab/SelectIoRxGearboxAligner-step-size

Notes:

Description

  • Ultrascale: CNTVALUEIN=dlyCfg(8 downto 0), 7-series: CNTVALUEIN=dlyCfg(8 downto 4)
  • DLY_STEP_SIZE_G can be set to 16 to improve the locking up duration for 7-series since the lower 4 bits on the dlyCfg bus are unused

adding EXT_QPLL_G generic to Gtpe2ChannelDummy.vhd
Author: Larry Ruckman [email protected]
Date: Thu Jun 3 12:25:42 2021 -0700
Pull: #865 (27 additions, 17 deletions, 1 files changed)
Branch: slaclab/Gtpe2ChannelDummy-ext-qpll

Notes:

Description

  • Adds support to use external QPLL
  • Example if when you have a mix of some GTPs used and other GTPs within the same QUAD

whitespace removal
Author: Larry Ruckman [email protected]
Date: Thu Jun 3 12:25:32 2021 -0700
Pull: #866 (15 additions, 15 deletions, 7 files changed)
Branch: slaclab/whitespace-removal

Notes:

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Patch Release v2.19.1

21 May 20:37
@slacrherbst slacrherbst
v2.19.1
c097ea7
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Patch Release v2.19.1

Pull Requests Since v2.19.0

Unlabeled

  1. #858 - adding TI TMP461
  2. #859 - AxiMicronN25Q.py Update

Pull Request Details

adding TI TMP461
Author: Larry Ruckman [email protected]
Date: Fri May 21 12:39:14 2021 -0700
Pull: #858 (498 additions, 0 deletions, 2 files changed)
Branch: slaclab/Tmp461

Notes:

Description

  • Developed and tested and migrated from slaclab/space-smurf-mcu

AxiMicronN25Q.py Update
Author: Larry Ruckman [email protected]
Date: Fri May 21 13:32:22 2021 -0700
Pull: #859 (67 additions, 47 deletions, 1 files changed)
Branch: slaclab/AxiMicronN25Q-password-lock-reg

Notes:

Description

  • Adding PasswordLock register
    • No longer can use _rawWrite for LSST for passwordLock + rogue v5
  • Code cleanup of the variables
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Minor Release v2.19.0

20 May 17:10
@slacrherbst slacrherbst
v2.19.0
36b7484
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Minor Release v2.19.0

Pull Requests Since v2.18.1

Unlabeled

  1. #848 - Release Candidate v2.19.0
  2. #853 - Adding complex DSP modules (requires VHDL-2008)
  3. #846 - adding support for SIMULATION_G in all GT dummy terminators
  4. #847 - Updates to Ultrascale+ GTY GbE
  5. #857 - CLINK Python SW Update for UART Messages
  6. #855 - Minor regression testing fixes and updates
  7. #852 - Updates to AxiDualPortRam.vhd and TrueDualPortRamXpm.vhd
  8. #854 - Some Module Reorganization
  9. #849 - Lmk04832 Pyrogue Update
  10. #856 - MmcmEmulation.vhd Update

Pull Request Details

adding support for SIMULATION_G in all GT dummy terminators
Author: Larry Ruckman [email protected]
Date: Wed May 12 09:42:14 2021 -0700
Pull: #846 (1545 additions, 1510 deletions, 5 files changed)
Branch: slaclab/TERM_GT_SIM

Notes:

Description

  • Not including the GT in simulation prevents the simulator to change the timebase from 1ps to 1fs step
  • I found myself doing this repeatably in multiple projects.
  • So it makes sense to integrate it into the module itself

Updates to Ultrascale+ GTY GbE
Author: Larry Ruckman [email protected]
Date: Thu May 13 09:06:36 2021 -0700
Pull: #847 (118 additions, 58 deletions, 4 files changed)
Branch: slaclab/GbE-gty-updates

Notes:

Description

  • adding support to Ultrascale+ GbE for customizing if FPGA doesn't have URAMs
    • Not all Ultrascale+ FPGAs have URAM (e.g. Artix Ultrascale+)

Release Candidate v2.19.0
Author: Larry Ruckman [email protected]
Date: Thu May 20 10:05:59 2021 -0700
Pull: #848 (5899 additions, 1623 deletions, 63 files changed)
Branch: slaclab/pre-release
Issues: #846, #847, #849, #852, #853, #854, #855, #856, #857

Notes:

Description

  • adding support for SIMULATION_G in all GT dummy terminators #846
  • Updates to Ultrascale+ GTY GbE #847
  • Lmk04832 Pyrogue Update #849
  • Updates to AxiDualPortRam.vhd and TrueDualPortRamXpm.vhd #852
  • Adding complex DSP modules (requires VHDL-2008) #853
  • Some Module Reorganization #854
  • Minor regression testing fixes and updates #855
  • MmcmEmulation.vhd Update #856
  • CLINK Python SW Update for UART Messages #857

Lmk04832 Pyrogue Update
Author: Larry Ruckman [email protected]
Date: Tue May 18 16:11:26 2021 -0700
Pull: #849 (13 additions, 3 deletions, 2 files changed)
Branch: slaclab/Lmk04832-pyrogue

Notes:

Description

  • Add debug messages to Lmx2615 hex loader

Updates to AxiDualPortRam.vhd and TrueDualPortRamXpm.vhd
Author: Larry Ruckman [email protected]
Date: Tue May 18 16:11:44 2021 -0700
Pull: #852 (21 additions, 3 deletions, 2 files changed)
Branch: slaclab/issue-851

Notes:

Description

  • Adding WRITE_MODE_G generic to TrueDualPortRamXpm.vhd
  • Adding assert for RAM memory configurations in AxiDualPortRam.vhd

Adding complex DSP modules (requires VHDL-2008)
Author: Larry Ruckman [email protected]
Date: Tue May 18 16:12:45 2021 -0700
Pull: #853 (4130 additions, 21 deletions, 34 files changed)
Branch: slaclab/fixed-2008

Notes:

Description

  • Update to surf/Makefile (GHDL)
  • Fixed bug in base/general/rtl/SlvDelayRam.vhd where the DELAY_G default value was out of range
  • In base/general/rtl/StdRtlPkg.vhd, adding logB, sort and median
  • Adding done port to base/general/tb/ClkRst.vhd
  • GHDL fix for base/sync/rtl/SynchronizerOneShot.vhd
  • Adding the following source code
    • base/general/rtl/LutFixedDelay.vhd
    • base/general/rtl/SlvFixedDelay.vhd
    • base/general/xilinx/Srl16Delay.vhd.
    • base/ram/xilinx/SinglePortRamPrimitive.vhd
    • dsp/core/ComplexFixedPkg.vhd
    • dsp/fixed/Add3.vhd
    • dsp/fixed/CfixedAccumulator.vhd
    • dsp/fixed/CfixedDelay.vhd
    • dsp/fixed/CfixedMult.vhd
    • dsp/fixed/CfixedMultAdd.vhd
    • dsp/fixed/CfixedPreAddMult.vhd
    • dsp/fixed/FirAverage.vhd
    • dsp/fixed/IirSimple.vhd
    • dsp/fixed/SfixedAccumulator.vhd
    • dsp/fixed/SfixedDelay.vhd
    • dsp/fixed/SfixedMult.vhd
    • dsp/fixed/SfixedMultAdd.vhd
    • dsp/fixed/SfixedPreAddMultAdd.vhd
    • dsp/fixed/SinCosLut.vhd
    • dsp/fixed/SinCosTaylor.vhd

Some Module Reorganization
Author: Larry Ruckman [email protected]
Date: Wed May 19 09:11:43 2021 -0700
Pull: #854 (15 additions, 1 deletions, 15 files changed)
Branch: slaclab/delay-reorg

Notes:

Description

  • delay module reorg
  • CRC module reorg

Minor regression testing fixes and updates
Author: Larry Ruckman [email protected]
Date: Thu May 20 08:45:52 2021 -0700
Pull: #855 (15 additions, 15 deletions, 5 files changed)
Branch: slaclab/regression-testing
Issues: #852

Notes:

Description

  • bug fix for AxiStreamMonAxiL.vhd when MEMORY_TYPE_G=distributed
    • Broke during PR #852
  • Fixed logB comments
  • renamed recently added port called 'done' to 'halt'

MmcmEmulation.vhd Update
Author: Larry Ruckman [email protected]
Date: Thu May 20 08:46:11 2021 -0700
Pull: #856 (1 additions, 1 deletions, 1 files changed)
Branch: slaclab/MmcmEmulation-update

Notes:

Description

  • emulate the LOCKED deasserting when RST is asserted

CLINK Python SW Update for UART Messages
Author: Larry Ruckman [email protected]
Date: Thu May 20 09:53:36 2021 -0700
Pull: #857 (61 additions, 33 deletions, 7 files changed)
Branch: slaclab/clink-uart-sw-msg

Notes:

Description

  • adding the device path to the UART printout
    • Useful information when you are operating with multiple cameras
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Patch Release v2.18.1

06 May 19:59
@slacrherbst slacrherbst
v2.18.1
f1683ac
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Patch Release v2.18.1

Pull Requests Since v2.18.0

Bug

  1. #844 - Dac38J84.yaml: Fix InitDac sequence

Unlabeled

  1. #845 - Release Candidate v2.18.1

Pull Request Details

Dac38J84.yaml: Fix InitDac sequence
Author: Larry Ruckman [email protected]
Date: Thu May 6 12:19:14 2021 -0700
Pull: #844 (6 additions, 2 deletions, 1 files changed)
Branch: slaclab/fix-dac38j84-yaml
Issues: #845
Labels: bug

Notes:

The register InitJesd was broken down into InitJesd and JesdRstN registers in #743, but the init sequence was not updated.

Description

@leosap reported that after the changes done in #743 the DAC were not properly initialized.

The issue was related to the register InitJesd (originally a 5-bit register) which was broken down into InitJesd(most significative 4 bits) and JesdRstN (less significative bit), but the InitDac was not updated accordingly.

This PR fixes that init sequence by using the new InitJesd and JesdRstN registers.

Release Candidate v2.18.1
Author: Larry Ruckman [email protected]
Date: Thu May 6 12:54:29 2021 -0700
Pull: #845 (6 additions, 2 deletions, 1 files changed)
Branch: slaclab/pre-release
Issues: #844

Notes:

Description

  • Dac38J84.yaml: Fix InitDac sequence #844
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Minor Release v2.18.0

05 May 18:01
@slacrherbst slacrherbst
v2.18.0
ee4f832
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Minor Release v2.18.0

Pull Requests Since v2.17.0

Unlabeled

  1. #842 - Release Candidate v2.18.0
  2. #840 - MicroblazeBasicCore Update
  3. #837 - Updates to DS2411Core and MicroblazeBasicCore
  4. #841 - Lmk04832 pyrogue
  5. #843 - Change counter increment logic to make GHDL bounds checking happy
  6. #839 - SpiSlave - Fix CPHA_G='0' corner case
  7. #838 - FirFilter - Fix incorrect range when truncating result

Pull Request Details

Updates to DS2411Core and MicroblazeBasicCore
Author: Larry Ruckman [email protected]
Date: Wed Apr 28 17:22:40 2021 -0700
Pull: #837 (1447 additions, 2705 deletions, 4 files changed)
Branch: slaclab/cPix_dev

Notes:

Description

  • The DS2411Core has IOBUF that will fail placement if unconnected or instantiated twice.
    • A copy of inout is needed in the application code.
  • Added support to MicroblazeBasicCore + AXIL_ADDR_SEL_C
    • Which enables full 4GB AXI-Lite support (instead of only 2GB of the 4GB, either upper or lower half)

FirFilter - Fix incorrect range when truncating result
Author: Larry Ruckman [email protected]
Date: Fri Apr 30 17:22:35 2021 -0700
Pull: #838 (2 additions, 2 deletions, 2 files changed)
Branch: slaclab/FirFilterFix

Notes:

Description

The FIR result truncation was off by one.

Now when I load a coefficient of 1.0 (actually .9999...) to a single tap and leave the other coefficients at 0.0, I get out the same thing that went in, as expected.

This change has been applied to both single and multi channel modules, but I've only tested the single channel.

SpiSlave - Fix CPHA_G='0' corner case
Author: Larry Ruckman [email protected]
Date: Fri Apr 30 17:22:55 2021 -0700
Pull: #839 (4 additions, 0 deletions, 1 files changed)
Branch: slaclab/SPI-fix

Notes:

Description

When CPHA_G='0', rdData must load into the shift register with 1 shift already applied.

MicroblazeBasicCore Update
Author: Larry Ruckman [email protected]
Date: Tue May 4 09:57:43 2021 -0700
Pull: #840 (15 additions, 6186 deletions, 7 files changed)
Branch: slaclab/MicroblazeBasicCoreWrapper-update
Issues: #837

Notes:

Description

  • Updating MicroblazeBasicCore Generic's to use _G coding style (instead of _C)
    • This may break some existing builds
  • latest MicroblazeBasicCore.bd was generated using 2020.1 (not 2018.3)
    • This also means the .bd files older than 2018.3 are broken because of new interface adding during PR #837, just removing them
    • Instead of rebuild all obsolete/legacy .bd files older than 2018.3 for PR #837, just removing them

Lmk04832 pyrogue
Author: Larry Ruckman [email protected]
Date: Fri Apr 30 15:54:29 2021 -0700
Pull: #841 (368 additions, 42 deletions, 8 files changed)
Branch: slaclab/Lmk04832-pyrogue

Notes:

Description

  • Update LMK/LMX PyRogue -- Add hex dump code loader.

Release Candidate v2.18.0
Author: Larry Ruckman [email protected]
Date: Wed May 5 10:56:56 2021 -0700
Pull: #842 (1831 additions, 8932 deletions, 21 files changed)
Branch: slaclab/pre-release
Issues: #837, #841, #838, #839, #840, #843

Notes:

Description

  • Updates to DS2411Core and MicroblazeBasicCore #837
  • Lmk04832 pyrogue #841
  • FirFilter - Fix incorrect range when truncating result #838
  • SpiSlave - Fix CPHA_G='0' corner case #839
  • MicroblazeBasicCore Update #840
  • Change counter increment logic to make GHDL bounds checking happy #843

Change counter increment logic to make GHDL bounds checking happy
Author: Larry Ruckman [email protected]
Date: Fri Apr 30 18:24:58 2021 -0700
Pull: #843 (3 additions, 5 deletions, 1 files changed)
Branch: slaclab/ghdl-sync-fix

Notes:

Description

GHDL complains about the counter incrementing beyond it's max bound without the else if statement.

Assets 2
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Minor Release v2.17.0

28 Apr 00:48
@slacrherbst slacrherbst
v2.17.0
e79af65
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Minor Release v2.17.0

Pull Requests Since v2.16.0

Unlabeled

  1. #835 - Release Candidate v2.17.0
  2. #834 - Adding 12 Gb/s and 15 Gb/s support to PGPv3/PGPv4
  3. #836 - Adding AxiLiteCrossbar.vhd generic checking

Pull Request Details

Adding 12 Gb/s and 15 Gb/s support to PGPv3/PGPv4
Author: Larry Ruckman [email protected]
Date: Tue Apr 27 16:30:34 2021 -0700
Pull: #834 (9180 additions, 108 deletions, 37 files changed)
Branch: slaclab/pgp4-15Gbps

Notes:

Description

  • Adding PGPv3/PGPv4 12Gb/s & 15 Gb/s support for the following FPGA configurations
    • Ultrascale+ GTY
    • Ultrascale+ GTH
    • Ultrascale GTH

Release Candidate v2.17.0
Author: Larry Ruckman [email protected]
Date: Tue Apr 27 17:43:51 2021 -0700
Pull: #835 (9184 additions, 108 deletions, 38 files changed)
Branch: slaclab/pre-release
Issues: #834, #836

Notes:

Description

  • Adding 12 Gb/s and 15 Gb/s support to PGPv3/PGPv4 #834
  • Adding AxiLiteCrossbar.vhd generic checking #836

Adding AxiLiteCrossbar.vhd generic checking
Author: Larry Ruckman [email protected]
Date: Tue Apr 27 17:43:37 2021 -0700
Pull: #836 (4 additions, 0 deletions, 1 files changed)
Branch: slaclab/AxiLiteCrossbar-error-check

Notes:

Description

  • Adding 'Mismatch between NUM_MASTER_SLOTS_G and MASTERS_CONFIG_G'length' error checking
Assets 2
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