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Patch Release v2.11.1

02 Nov 21:57
@ruck314 ruck314
v2.11.1
bc0632e
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Patch Release v2.11.1

Pull Requests Since v2.11.0

Unlabeled

  1. #763 - Release Candidate v2.11.1
  2. #762 - Update SaltRx.vhd

Pull Request Details

Update SaltRx.vhd
Author: Larry Ruckman [email protected]
Date: Tue Oct 27 22:16:36 2020 -0700
Pull: #762 (1 additions, 1 deletions, 1 files changed)
Branch: slaclab/Salt-RX-ssi-FIFO

Notes:

Description

  • VALID_THOLD_G = 0
    • 0 = cache frame before SSI outbound filter check

Release Candidate v2.11.1
Author: Larry Ruckman [email protected]
Date: Mon Nov 2 13:00:31 2020 -0800
Pull: #763 (1 additions, 1 deletions, 1 files changed)
Branch: slaclab/pre-release
Issues: #762

Notes:

Description

  • Update SaltRx.vhd #762
Assets 2
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Minor Release v2.11.0

27 Oct 00:54
@ruck314 ruck314
v2.11.0
ce09733
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Minor Release v2.11.0

Pull Requests Since v2.10.0

Bug

  1. #755 - adding missing AdcTester to _Ad9249.py
  2. #756 - _Ad9249.py: resolve special characters and non numeric key errors

Enhancement

  1. #758 - Updates to Gearbox and SSP
  2. #759 - OutputBufferReg.vhd Update

Unlabeled

  1. #757 - Release Candidate v2.11.0
  2. #760 - adding protocols/pgp/pgp2b/gtyUltraScale+
  3. #761 - FIR Filter Development

Pull Request Details

adding missing AdcTester to _Ad9249.py
Author: Larry Ruckman [email protected]
Date: Thu Oct 1 10:29:38 2020 -0700
Pull: #755 (113 additions, 0 deletions, 1 files changed)
Branch: slaclab/ad9249-StreamPatternTester-py
Labels: bug

Notes:

_Ad9249.py: resolve special characters and non numeric key errors
Author: Larry Ruckman [email protected]
Date: Wed Oct 7 12:58:44 2020 -0700
Pull: #756 (37 additions, 17 deletions, 1 files changed)
Branch: slaclab/ESCORE-592
Jira: https://jira.slac.stanford.edu/issues/ESCORE-592
Labels: bug

Notes:

Description

  • Changed DevIndexMask[7:0] to DevIndexMask_DataCh[0] and DevIndexMask_DataCh[1]
  • Changed DevIndexMask[DCO:FCO] to DevIndexMask_DCO and DevIndexMask_FCO
  • Changed Ad9249Chip[{i}].BankConfig[0] to Ad9249ChipBankConfig0[{i}]
  • Changed Ad9249Chip[{i}].BankConfig[1] to Ad9249ChipBankConfig1[{i}]
  • Resolves these warning messages ...
$ ipython -- scripts/EpixDaqGen2Gui.py --dev=sim
Rogue/pyrogue version v5.4.0-27-gfafb7a44. https://github.com/slaclab/rogue
WARNING:pyrogue.Device.Ad9249ConfigGroup.Ad9249Chip[0].BankConfig[0]:Node DevIndexMask[7:0] with one or more special characters will cause lookup errors.
WARNING:pyrogue.Device.Ad9249ConfigGroup.Ad9249Chip[0].BankConfig[0]:Array node DevIndexMask[7:0] with non numeric key will cause lookup errors.
WARNING:pyrogue.Device.Ad9249ConfigGroup.Ad9249Chip[0].BankConfig[0]:Node DevIndexMask[DCO:FCO] with one or more special characters will cause lookup errors.
WARNING:pyrogue.Device.Ad9249ConfigGroup.Ad9249Chip[0].BankConfig[0]:Array node DevIndexMask[DCO:FCO] with non numeric key will cause lookup errors.
WARNING:pyrogue.Device.Ad9249Config.Ad9249Config:Node Ad9249Chip[0].BankConfig[0] with one or more special characters will cause lookup errors.
WARNING:pyrogue.Device.Ad9249Config.Ad9249Config:Array node Ad9249Chip[0].BankConfig[0] with non numeric key will cause lookup errors.
WARNING:pyrogue.Device.Ad9249ConfigGroup.Ad9249Chip[0].BankConfig[1]:Node DevIndexMask[7:0] with one or more special characters will cause lookup errors.
WARNING:pyrogue.Device.Ad9249ConfigGroup.Ad9249Chip[0].BankConfig[1]:Array node DevIndexMask[7:0] with non numeric key will cause lookup errors.
WARNING:pyrogue.Device.Ad9249ConfigGroup.Ad9249Chip[0].BankConfig[1]:Node DevIndexMask[DCO:FCO] with one or more special characters will cause lookup errors.
WARNING:pyrogue.Device.Ad9249ConfigGroup.Ad9249Chip[0].BankConfig[1]:Array node DevIndexMask[DCO:FCO] with non numeric key will cause lookup errors.
WARNING:pyrogue.Device.Ad9249Config.Ad9249Config:Node Ad9249Chip[0].BankConfig[1] with one or more special characters will cause lookup errors.
WARNING:pyrogue.Device.Ad9249Config.Ad9249Config:Array node Ad9249Chip[0].BankConfig[1] with non numeric key will cause lookup errors.
WARNING:pyrogue.Device.Ad9249ConfigGroup.Ad9249Chip[1].BankConfig[0]:Node DevIndexMask[7:0] with one or more special characters will cause lookup errors.
WARNING:pyrogue.Device.Ad9249ConfigGroup.Ad9249Chip[1].BankConfig[0]:Array node DevIndexMask[7:0] with non numeric key will cause lookup errors.
WARNING:pyrogue.Device.Ad9249ConfigGroup.Ad9249Chip[1].BankConfig[0]:Node DevIndexMask[DCO:FCO] with one or more special characters will cause lookup errors.
WARNING:pyrogue.Device.Ad9249ConfigGroup.Ad9249Chip[1].BankConfig[0]:Array node DevIndexMask[DCO:FCO] with non numeric key will cause lookup errors.
WARNING:pyrogue.Device.Ad9249Config.Ad9249Config:Node Ad9249Chip[1].BankConfig[0] with one or more special characters will cause lookup errors.
WARNING:pyrogue.Device.Ad9249Config.Ad9249Config:Array node Ad9249Chip[1].BankConfig[0] with non numeric key will cause lookup errors.
WARNING:pyrogue.Device.Ad9249ConfigGroup.Ad9249Chip[1].BankConfig[1]:Node DevIndexMask[7:0] with one or more special characters will cause lookup errors.
WARNING:pyrogue.Device.Ad9249ConfigGroup.Ad9249Chip[1].BankConfig[1]:Array node DevIndexMask[7:0] with non numeric key will cause lookup errors.
WARNING:pyrogue.Device.Ad9249ConfigGroup.Ad9249Chip[1].BankConfig[1]:Node DevIndexMask[DCO:FCO] with one or more special characters will cause lookup errors.
WARNING:pyrogue.Device.Ad9249ConfigGroup.Ad9249Chip[1].BankConfig[1]:Array node DevIndexMask[DCO:FCO] with non numeric key will cause lookup errors.
WARNING:pyrogue.Device.Ad9249Config.Ad9249Config:Node Ad9249Chip[1].BankConfig[1] with one or more special characters will cause lookup errors.
WARNING:pyrogue.Device.Ad9249Config.Ad9249Config:Array node Ad9249Chip[1].BankConfig[1] with non numeric key will cause lookup errors.

Release Candidate v2.11.0
Author: Larry Ruckman [email protected]
Date: Mon Oct 26 15:01:21 2020 -0700
Pull: #757 (3261 additions, 420 deletions, 29 files changed)
Branch: slaclab/pre-release
Issues: #755, #756, #758, #759, #760, #761
Labels: release

Notes:

Description

  • adding missing AdcTester to _Ad9249.py #755
  • _Ad9249.py: resolve special characters and non numeric key errors #756
  • Updates to Gearbox and SSP #758
  • OutputBufferReg.vhd Update #759
  • adding protocols/pgp/pgp2b/gtyUltraScale+ #760
  • FIR Filter Development #761

Updates to Gearbox and SSP
Author: Larry Ruckman [email protected]
Date: Wed Oct 14 12:10:59 2020 -0700
Pull: #758 (133 additions, 85 deletions, 8 files changed)
Branch: slaclab/SelectioDeser-dev
Labels: enhancement

Notes:

Description

  • adding ability to dynamically change the gearbox's bit order inbound/outbound
  • adding GearboxSlaveBitOrder & GearboxMasterBitOrder registers to SspLowSpeedDecoderReg

OutputBufferReg.vhd Update
Author: Larry Ruckman [email protected]
Date: Thu Oct 15 22:09:01 2020 -0700
Pull: #759 (1 additions, 2 deletions, 1 files changed)
Branch: slaclab/OutputBufferReg-update
Labels: enhancement

Notes:

Description

  • updating the defautl to same edge because 99% of the time only rising edge
    • Helps making timing because not using falling edge
  • ... And because ODDR.D1 and ODDR.D2 tied together

adding protocols/pgp/pgp2b/gtyUltraScale+
Author: Larry Ruckman [email protected]
Date: Mon Oct 26 10:36:15 2020 -0700
Pull: #760 (1909 additions, 5 deletions, 7 files changed)
Branch: slaclab/pgp2b-gty

Notes:

Description

  • PGP2b GTY support for Kintex Ultrascale+ and Virtex Ultrascale+

FIR Filter Development
Author: Larry Ruckman [email protected]
Date: Mon Oct 26 14:44:07 2020 -0700
Pull: #761 (1068 additions, 311 deletions, 12 files changed)
Branch: slaclab/fir-dev

Notes:

Description

  • Adding Finite Impulse Response (FIR) Filter
    • With support for parallel channel processing and time multiplexing
  • combining DualPortRam & OctalPortRam in LutRam
    • DualPortRam using LUTRAM was not optimizing the 2 unused ports on the QuadLutRam, which is why I made this change
Assets 2
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Minor Release v2.10.0

30 Sep 23:18
@ruck314 ruck314
v2.10.0
081638c
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Minor Release v2.10.0

Pull Requests Since v2.9.2

Bug

  1. #754 - Updates for SelectioDeser7Series.vhd and Ad9249ReadoutGroup.vhd
  2. #751 - Update _AxiVersion.py

Enhancement

  1. #747 - General PGP Development Updates

Unlabeled

  1. #753 - Release Candidate v2.10.0

Pull Request Details

General PGP Development Updates
Author: Larry Ruckman [email protected]
Date: Tue Sep 29 09:17:23 2020 -0700
Pull: #747 (696 additions, 14 deletions, 17 files changed)
Branch: slaclab/pgp-fifos
Labels: enhancement

Notes:

Description

  • adding common PGP VC FIFOs that can be used for all versions of PGP
    • Works for PGPv2b, PGPv3 and PGP-ETH
  • Switching to surf.AxiStreamGearbox for commonly used AxiStream FIFOs resizing
    • surf.AxiStreamGearbox will use surf.AxiStreamResize if bus multiple
    • Required for my resizing of 80-bit and 96-bit AXI streams before/after the PGP VC FIFOs
  • adding xilinx/UltraScale+/clocking/rtl/ClockManagerUltraScale.vhd
    • required for CLKFBOUT_MULT_F_G = 128.0 using the MMCME4_ADV primitive (instead of MMCME3_ADV)
  • updates to PgpEthCaui4Gty to help make timing
  • Misc. whitespace removal

Update _AxiVersion.py
Author: Larry Ruckman [email protected]
Date: Thu Sep 24 12:04:22 2020 -0700
Pull: #751 (7 additions, 1 deletions, 1 files changed)
Branch: slaclab/AxiVersion-py-update
Labels: bug

Notes:

Description

  • Fixed Surf.AxiVersion.Builder
    • Sometimes there is padding and sometimes there is not

Release Candidate v2.10.0
Author: Larry Ruckman [email protected]
Date: Wed Sep 30 16:15:18 2020 -0700
Pull: #753 (711 additions, 20 deletions, 23 files changed)
Branch: slaclab/pre-release
Issues: #751, #754, #747
Labels: release

Notes:

Description

  • Update _AxiVersion.py #751
  • Updates for SelectioDeser7Series.vhd and Ad9249ReadoutGroup.vhd #754
  • General PGP Development Updates #747

Updates for SelectioDeser7Series.vhd and Ad9249ReadoutGroup.vhd
Author: Larry Ruckman [email protected]
Date: Tue Sep 29 09:14:33 2020 -0700
Pull: #754 (9 additions, 7 deletions, 6 files changed)
Branch: slaclab/SelectioDeser7Series-bug-fix
Labels: bug

Notes:

Description

  • Updates for SelectioDeser7Series.vhd
    • Fixed bug where IODELAY_GROUP_G & REF_FREQ_G was not being propagated to lower modules
    • bug fix for clk/rst swap
  • bug fix for Ad9249ReadoutGroup.vhd (7Series/UltraScale)
Assets 2
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Patch Release v2.9.2

17 Sep 02:23
@ruck314 ruck314
v2.9.2
b79ce5b
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Patch Release v2.9.2

Pull Requests Since v2.9.1

Unlabeled

  1. #750 - Release Candidate v2.9.2

Pull Request Details

Release Candidate v2.9.2
Author: Larry Ruckman [email protected]
Date: Wed Sep 16 19:16:45 2020 -0700
Pull: #750 (12 additions, 1 deletions, 3 files changed)
Branch: slaclab/pre-release

Notes:

Description

  • bug fix for v2.9.1 release
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Patch Release v2.9.1

17 Sep 01:47
@ruck314 ruck314
v2.9.1
d25ff35
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Patch Release v2.9.1

Pull Requests Since v2.9.0

Unlabeled

  1. #749 - Release Candidate v2.9.1
  2. #748 - Jesd204bPkg.invData bug fix

Pull Request Details

Jesd204bPkg.invData bug fix
Author: Larry Ruckman [email protected]
Date: Wed Sep 16 18:10:35 2020 -0700
Pull: #748 (1 additions, 0 deletions, 1 files changed)
Branch: slaclab/ESLMPS-94
Jira: https://jira.slac.stanford.edu/issues/ESLMPS-94

Notes:

Description

  • Correct for a +1 offset when using the Jesd204bPkg.invData function

JIRA

ESLMPS-94

Release Candidate v2.9.1
Author: Larry Ruckman [email protected]
Date: Wed Sep 16 18:42:55 2020 -0700
Pull: #749 (1 additions, 0 deletions, 1 files changed)
Branch: slaclab/pre-release
Issues: #748

Notes:

Description

  • Jesd204bPkg.invData bug fix #748
Assets 2
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Minor Release v2.9.0

01 Sep 16:52
@ruck314 ruck314
v2.9.0
41c675d
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Minor Release v2.9.0

Pull Requests Since v2.8.1

Bug

  1. #741 - Bug fix for AxiStreamDmaRead.vhd and AxiStreamDmaWrite.vhd

Enhancement

  1. #746 - Ip integrator Support
  2. #739 - adding AxiMonAxiL and AxiRateGen
  3. #745 - adding AxiStreamGearbox.vhd
  4. #742 - Adding TPD_G support to XPM RAMs
  5. #744 - JesdTx Update

Unlabeled

  1. #740 - Release Candidate v2.9.0
  2. #743 - Update Dac38J84 CPSW YAML definition
  3. #732 - Bring out SYNTH_MODE_G generic for internal RAMs

Pull Request Details

Bring out SYNTH_MODE_G generic for internal RAMs
Author: Larry Ruckman [email protected]
Date: Mon Aug 31 15:56:28 2020 -0700
Pull: #732 (178 additions, 128 deletions, 18 files changed)
Branch: slaclab/synth_mode_g

Notes:

Description

This PR exposes the SYNTH_MOD_G generic from internal RAMs in modules where it makes sense to have this configurable.

Details

For Xilinx builds, the SYNTH_MOD_G => "xpm" option seems to provide much better timing closure for very large RAMs compared to "inferred". It is useful to therefore to make the option available when possible.

adding AxiMonAxiL and AxiRateGen
Author: Larry Ruckman [email protected]
Date: Fri Aug 14 16:22:33 2020 -0700
Pull: #739 (751 additions, 63 deletions, 10 files changed)
Branch: slaclab/axi4-monitor
Labels: enhancement

Notes:

Description

  • Re-propose the existing AXI stream monitor as a AXI4 memory monitor
  • Adding AxiRateGen, which support programmable read/write burst rate and frame size

Release Candidate v2.9.0
Author: Larry Ruckman [email protected]
Date: Tue Sep 1 09:48:25 2020 -0700
Pull: #740 (3324 additions, 422 deletions, 52 files changed)
Branch: slaclab/pre-release
Issues: #739, #741, #742, #743, #744, #745, #746, #732
Labels: release

Notes:

Description

  • adding AxiMonAxiL and AxiRateGen #739
  • Bug fix for AxiStreamDmaRead.vhd and AxiStreamDmaWrite.vhd #741
  • Adding TPD_G support to XPM RAMs #742
  • Update Dac38J84 CPSW YAML definition #743
  • JesdTx Update #744
  • adding AxiStreamGearbox.vhd #745
  • Ip integrator Support #746
  • Bring out SYNTH_MODE_G generic for internal RAMs #732

Bug fix for AxiStreamDmaRead.vhd and AxiStreamDmaWrite.vhd
Author: Larry Ruckman [email protected]
Date: Mon Aug 17 08:20:15 2020 -0700
Pull: #741 (6 additions, 2 deletions, 2 files changed)
Branch: slaclab/dma-v1-bug-fix
Labels: bug

Notes:

Description

  • bug fix for super wide AXI4 memory bus (> 128-bits) and bypassing AxiStreamShift.vhd

Adding TPD_G support to XPM RAMs
Author: Larry Ruckman [email protected]
Date: Fri Aug 21 13:25:45 2020 -0700
Pull: #742 (13 additions, 5 deletions, 2 files changed)
Branch: slaclab/xpm-ram-TPD_G
Labels: enhancement

Notes:

Description

  • similar to the XPM FIFOs, adding TPD_G output delay to XPM RAMs
  • TPD_G makes viewing the simulation behavior a lot easier

Update Dac38J84 CPSW YAML definition
Author: Larry Ruckman [email protected]
Date: Thu Aug 20 14:57:32 2020 -0700
Pull: #743 (249 additions, 222 deletions, 1 files changed)
Branch: slaclab/ESLCOMMON-245
Jira: https://jira.slac.stanford.edu/issues/ESLCOMMON-245

Notes:

Update the Dac38J84 YAML definition, based on the definition used by Rogue's device.

Description

The Dac38J84 YAML definition is not up to date with the latest changes done in the Rogue version. So, this PR updates this definition. It mainly:

  • Add the missing JesdRstN register,
  • Adds the NcoSync command,
  • Adds a missing register in the ClearAlarms command, and
  • Breaks down the ID register into VersionId and VendorId.

It also change the formatting for better readability.

JIRA

https://jira.slac.stanford.edu/browse/LIMRLLRF-17

JesdTx Update
Author: Larry Ruckman [email protected]
Date: Thu Aug 27 08:54:07 2020 -0700
Pull: #744 (6 additions, 2 deletions, 2 files changed)
Branch: slaclab/ESCRYODET-710
Jira: https://jira.slac.stanford.edu/issues/ESCRYODET-710
Labels: enhancement

Notes:

Description

  • adding dacReady_o to JESD TX

adding AxiStreamGearbox.vhd
Author: Larry Ruckman [email protected]
Date: Thu Aug 27 09:23:09 2020 -0700
Pull: #745 (371 additions, 0 deletions, 1 files changed)
Branch: slaclab/axis-gearbox
Labels: enhancement

Notes:

Description

  • This module is based on AxiStreamResize.vhd and Gearbox.vhd
  • Unlike AxiStreamResize.vhd which only supports resizing of word multiple, AxiStreamGearbox.vhd can resize any byte width to any byte width
    • tDests interleaving still not supported
  • I have benchmarked the resources to the Xilinx IP core for resizing and AxiStreamGearbox.vhd uses about half as many LUTs as the IP core.

Ip integrator Support
Author: Larry Ruckman [email protected]
Date: Fri Aug 28 09:15:37 2020 -0700
Pull: #746 (1750 additions, 0 deletions, 16 files changed)
Branch: slaclab/ip_integrator-update
Labels: enhancement

Notes:

Description

  • Adding Ip integrator Support
    • axi/axi-lite/ip_integrator/AxiVersionIpIntegrator.vhd
    • axi/axi-lite/ip_integrator/AxiDualPortRamIpIntegrator.vhd
    • axi/axi-lite/ip_integrator/MasterAxiLiteIpIntegrator.vhd
    • AxiDualPortRamIpIntegrator.vhd: Wrapper on AxiDualPortRam
    • axi/axi-lite/ip_integrator/SlaveAxiLiteIpIntegrator.vhd
    • axi/axi-stream/ip_integrator/MasterAxiStreamTerminateIpIntegrator.vhd
    • axi/axi-stream/ip_integrator/SlaveAxiStreamTerminateIpIntegrator.vhd
    • axi/axi-stream/ip_integrator/MasterAxiStreamIpIntegrator.vhd
    • axi/axi-stream/ip_integrator/SlaveAxiStreamIpIntegrator.vhd
    • base/general/ip_integrator/MasterRamIpIntegrator.vhd
    • base/general/ip_integrator/SlaveRamIpIntegrator.vhd
Assets 2
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Patch Release v2.8.1

06 Aug 22:59
@ruck314 ruck314
v2.8.1
55450a7
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Patch Release v2.8.1

Pull Requests Since v2.8.0

Bug

  1. #738 - Fix anaconda build

Unlabeled

  1. #729 - Release Candidate v2.8.1
  2. #737 - Replacing custom gearbox causing issues in ad9249 deserializer of the Ultrascale architecture
  3. #734 - SspDeframer Update
  4. #727 - adding general purpose RTL MUX
  5. #735 - RogueTcpStreamWrap.vhd Update
  6. #726 - adding force termination feature to AxiStreamBatcher
  7. #733 - Updating SPI PROMs' addrMode default 32-bits mode
  8. #728 - Update Pgp3Gtx7Wrapper.vhd
  9. #736 - Fixed bug where PGP RX TDEST alaways zero and not VC index for VCS simulation
  10. #730 - updates to CLINK python for dual CH support
  11. #731 - Update error report message
  12. #724 - Updating SW Default for ClinkChannel.SerThrottle
  13. #725 - fixed bug where SerThrottle SW init value would overwrite DataEn

Pull Request Details

Updating SW Default for ClinkChannel.SerThrottle
Author: Larry Ruckman [email protected]
Date: Tue Jul 21 09:45:25 2020 -0700
Pull: #724 (1 additions, 1 deletions, 1 files changed)
Branch: slaclab/ClinkChannel-SerThrottle

Notes:

Description

fixed bug where SerThrottle SW init value would overwrite DataEn
Author: Larry Ruckman [email protected]
Date: Thu Jul 23 09:52:57 2020 -0700
Pull: #725 (0 additions, 1 deletions, 1 files changed)
Branch: slaclab/clink-DataEn

Notes:

Description

  • Fixes in the issue in the short term
  • In the long term, we should redo the register mapping to be 1 R/W (or WO) per 32-bit boundary

adding force termination feature to AxiStreamBatcher
Author: Larry Ruckman [email protected]
Date: Thu Jul 23 20:35:51 2020 -0700
Pull: #726 (29 additions, 13 deletions, 2 files changed)
Branch: slaclab/ESCORE-586
Jira: https://jira.slac.stanford.edu/issues/ESCORE-586

Notes:

Description

  • This will prevent a partial frame leaking into the first super frame after a AxiStreamBatcherEventBuilder's blowoff

adding general purpose RTL MUX
Author: Larry Ruckman [email protected]
Date: Mon Jul 27 11:00:33 2020 -0700
Pull: #727 (107 additions, 0 deletions, 1 files changed)
Branch: slaclab/rtl-mux

Notes:

Description

  • Used when you want to force inference of F7MUX, F8MUX and F9MUX primitives to save CLB LUTs.

Update Pgp3Gtx7Wrapper.vhd
Author: Larry Ruckman [email protected]
Date: Mon Jul 27 16:22:36 2020 -0700
Pull: #728 (4 additions, 4 deletions, 2 files changed)
Branch: slaclab/Pgp3Gtx7Wrapper-patch

Notes:

Description

  • GTX (not GTH) for Pgp3Gtx7Wrapper.vhd
  • GTP (not GTH) for Pgp3Gtp7Wrapper.vhd
  • Changing from "EN_GTH_DRP_G" to "EN_GT_DRP_G" for both modules

Release Candidate v2.8.1
Author: Larry Ruckman [email protected]
Date: Thu Aug 6 15:55:50 2020 -0700
Pull: #729 (530 additions, 1266 deletions, 22 files changed)
Branch: slaclab/pre-release
Issues: #724, #725, #726, #727, #728, #730, #731, #733, #735, #734, #736, #737, #738

Notes:

Description

  • Updating SW Default for ClinkChannel.SerThrottle #724
  • fixed bug where SerThrottle SW init value would overwrite DataEn #725
  • adding force termination feature to AxiStreamBatcher #726
  • adding general purpose RTL MUX #727
  • Update Pgp3Gtx7Wrapper.vhd #728
  • updates to CLINK python for dual CH support #730
  • Update error report message #731
  • Updating SPI PROMs' addrMode default 32-bits mode #733
  • RogueTcpStreamWrap.vhd Update #735
  • SspDeframer Update #734
  • Fixed bug where PGP RX TDEST alaways zero and not VC index for VCS simulation #736
  • Replacing custom gearbox causing issues in ad9249 deserializer of the Ultrascale architecture #737
  • Fix anaconda build #738

updates to CLINK python for dual CH support
Author: Larry Ruckman [email protected]
Date: Thu Jul 30 13:40:10 2020 -0700
Pull: #730 (3 additions, 2 deletions, 2 files changed)
Branch: slaclab/clink-dual-ch

Notes:

Description

  • Required changes to support ClinkFebPgp2b_2ch FW build

Update error report message
Author: Larry Ruckman [email protected]
Date: Thu Jul 30 13:22:04 2020 -0700
Pull: #731 (1 additions, 1 deletions, 1 files changed)
Branch: slaclab/error-report-fix

Notes:

Description

An error report in AxiStreamResize was reporting as an AxiStreamFifoV2 error.

Updating SPI PROMs' addrMode default 32-bits mode
Author: Larry Ruckman [email protected]
Date: Fri Jul 31 13:00:38 2020 -0700
Pull: #733 (14 additions, 9 deletions, 2 files changed)
Branch: slaclab/PROM-32-bit-default

Notes:

Description

  • This is a much better default since 99% of all our SPI PROMs > 24-bits of address
    • I (and others) have been burnt too many times having the default set to 24-bits
  • Updating CypressS25Fl.py's addrMode default to true (32-bits mode)
    • Including bug fix for CypressS25Fl and 32-bit address mode
  • Updating AxiMicronN25Q.py's addrMode default to true (32-bits mode)

SspDeframer Update
Author: Larry Ruckman [email protected]
Date: Mon Aug 3 14:28:21 2020 -0700
Pull: #734 (72 additions, 58 deletions, 4 files changed)
Branch: slaclab/cryo-deframer

Notes:

Description

  • changing the deframer to continue the frame in case an invalid code is received during data transmission. Generic BRK_FRAME_ON_ERROR keeps behavior compatibility with present behavior.

RogueTcpStreamWrap.vhd Update
Author: Larry Ruckman [email protected]
Date: Mon Aug 3 14:28:31 2020 -0700
Pull: #735 (37 additions, 23 deletions, 1 files changed)
Branch: slaclab/RogueTcpStreamWrap-update

Notes:

Description

  • Prevent dropping non-zero TDEST frames at the RogueTcpStreamWrap.AxiStreamDemux for interleave applications that use multiple RogueTcpStreamWrap modules with CHAN_COUNT_G=1

Fixed bug where PGP RX TDEST alaways zero and not VC index for VCS simulation
Author: Larry Ruckman [email protected]
Date: Tue Aug 4 15:53:23 2020 -0700
Pull: #736 (4 additions, 1 deletions, 3 files changed)
Branch: slaclab/pgp-sim-rx-tdest

Notes:

Description

  • Added TDEST_MASK_G to RogueTcpStreamWrap.vhd to set the outbound AXI stream's DEST when CHAN_COUNT_G=1
  • Then set TDEST_MASK_G = VC index in the PGP wrappers

Replacing custom gearbox causing issues in ad9249 deserializer of the Ultrascale architecture
Author: Larry Ruckman [email protected]
Date: Thu Aug 6 09:44:29 2020 -0700
Pull: #737 (257 additions, 1152 deletions, 3 files changed)
Branch: slaclab/epix-dev2

Notes:

Replacing custom gearbox causing issues in ad9249 deserializer of the Ultrascale architecture.

Fix anaconda build
Author: Larry Ruckman [email protected]
Date: Thu Aug 6 15:28:14 2020 -0700
Pull: #738 (2 additions, 2 deletions, 2 files changed)
Branch: slaclab/fix_conda
Labels: bug

Notes:

Attempt to fix anaconda build by limiting build python version to less than 3.8. I have left the run limitation open to see if this works.

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Minor Release v2.8.0

20 Jul 19:09
@ruck314 ruck314
v2.8.0
69df912
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Minor Release v2.8.0

Pull Requests Since v2.7.0

Unlabeled

  1. #722 - Release Candidate v2.8.0
  2. #719 - Update to SURF's UART
  3. #718 - Resolving AXI-Lite Protocol Violations in the AxiLitePkg.vhd
  4. #721 - AXI-Lite Logic Optimization for reads
  5. #723 - SyncMinMax and AxiStreamBatcherEventBuilder Bug fixes
  6. #720 - Fixed Surf.AxiVersion.Builder

Pull Request Details

Resolving AXI-Lite Protocol Violations in the AxiLitePkg.vhd
Author: Larry Ruckman [email protected]
Date: Fri Jul 17 10:51:41 2020 -0700
Pull: #718 (50 additions, 35 deletions, 7 files changed)
Branch: slaclab/ESCORE-581
Jira: https://jira.slac.stanford.edu/issues/ESCORE-581

Notes:

Description

  • resolved AXI-Lite protocol violation = AXI_ERRS_BRESP_AW for axiSlaveWriteResponse()
  • resolved AXI-Lite protocol violation = AXI_AUXM_RCAM_UNDERFLOW for axiSlaveReadResponse()
  • resolved AXI-Lite protocol violation = AXI_AUXM_RCAM_UNDERFLOW for axiSlaveDefault()
  • Update to axiSlaveReadResponse() and axiSlaveWaitReadTxn() requires rdata not to be modified outside of axilStatus.readEnable=0x1
  • whitespace removal on AxiLiteCrossbar.vhd

Simulation Testbed

https://github.com/slaclab/surf-axi-protocol-checking/blob/master/firmware/simulations/SurfAxiLiteProtocolCheckerTb/tb/SurfAxiLiteProtocolCheckerTb.vhd

Update to SURF's UART
Author: Larry Ruckman [email protected]
Date: Fri Jul 17 10:40:37 2020 -0700
Pull: #719 (130 additions, 130 deletions, 5 files changed)
Branch: slaclab/ESCORE-576
Jira: https://jira.slac.stanford.edu/issues/ESCORE-576

Notes:

Description

  • relabel clkEn to baudClkEn
    • because it is not a clock enable but a heartbeat strobe

Fixed Surf.AxiVersion.Builder
Author: Larry Ruckman [email protected]
Date: Fri Jul 17 11:16:49 2020 -0700
Pull: #720 (1 additions, 1 deletions, 1 files changed)
Branch: slaclab/ESCORE-579
Jira: https://jira.slac.stanford.edu/issues/ESCORE-579

Notes:

Description

Parsing before fix:

AxiVersion:
  BuildStamp: "Kcu105GigE: Vivado v2020.1, rdsrv302 (x86_64), Built Thu 16 Jul\
    \ 2020 11:56:02 AM PDT by ruckman\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\
    \0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\
    \0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\
    \0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\
    \0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0"
  ImageName: Kcu105GigE
  BuildEnv: Vivado v2020.1
  BuildServer: rdsrv302 (x86_64)
  BuildDate: Thu 16 Jul 2020 11:56:02 AM PDT
  Builder: "ruckman\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\
    \0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\
    \0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\
    \0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\
    \0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0"

Parsing after fix:

AxiVersion:
  BuildStamp: "Kcu105GigE: Vivado v2020.1, rdsrv302 (x86_64), Built Thu 16 Jul\
    \ 2020 11:56:02 AM PDT by ruckman\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\
    \0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\
    \0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\
    \0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\
    \0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0"
  ImageName: Kcu105GigE
  BuildEnv: Vivado v2020.1
  BuildServer: rdsrv302 (x86_64)
  BuildDate: Thu 16 Jul 2020 11:56:02 AM PDT
  Builder: ruckman

AXI-Lite Logic Optimization for reads
Author: Larry Ruckman [email protected]
Date: Fri Jul 17 10:35:11 2020 -0700
Pull: #721 (3 additions, 42 deletions, 26 files changed)
Branch: slaclab/ESCORE-582
Jira: https://jira.slac.stanford.edu/issues/ESCORE-582

Notes:

Description

  • rdata is already reset to zero in axiSlaveWaitTxn.axiSlaveWaitReadTxn()

Release Candidate v2.8.0
Author: Larry Ruckman [email protected]
Date: Mon Jul 20 12:03:50 2020 -0700
Pull: #722 (197 additions, 204 deletions, 36 files changed)
Branch: slaclab/pre-release
Issues: #721, #719, #718, #720, #723

Notes:

New Features

  • AXI-Lite Logic Optimization for reads #721
  • Update to SURF's UART #719

Bug Fixes

  • Resolving AXI-Lite Protocol Violations in the AxiLitePkg.vhd #718
  • Fixed Surf.AxiVersion.Builder #720
  • SyncMinMax and AxiStreamBatcherEventBuilder Bug fixes #723

SyncMinMax and AxiStreamBatcherEventBuilder Bug fixes
Author: Larry Ruckman [email protected]
Date: Mon Jul 20 09:49:31 2020 -0700
Pull: #723 (16 additions, 6 deletions, 2 files changed)
Branch: slaclab/SyncMinMax-bug-fix
Issues: #718

Notes:

Description

  • bug fix for dataOut when rstStat event occurs
  • bug fix for AxiStreamBatcherEventBuilder's AXI-Lite after PR #718
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Minor Release v2.7.0

17 Jul 00:00
@ruck314 ruck314
v2.7.0
78450fd
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Minor Release v2.7.0

Pull Requests Since v2.6.7

Enhancement

  1. #707 - Allow per destination buffer limits in DMA engine

Unlabeled

  1. #708 - Release Candidate v2.7.0
  2. #711 - Adding SlvDelayRam.vhd
  3. #710 - AxiStreamDmaV2Desc.vhd Updates
  4. #713 - Bug fixes for UartTx.vhd & ClinkUart.vhd
  5. #712 - Fix AXI-Lite protocol error in AxiLiteCrossbar
  6. #715 - Removing Accidental Commit of Python Debugger By User
  7. #717 - Fixed typo in ClinkChannel.py
  8. #709 - Update _EM22xx.py

Pull Request Details

Allow per destination buffer limits in DMA engine
Author: Larry Ruckman [email protected]
Date: Thu Jul 9 17:27:59 2020 -0700
Pull: #707 (147 additions, 26 deletions, 6 files changed)
Branch: slaclab/dest_buffer_limits
Labels: enhancement

Notes:

The goal of this PR is to allow a limit on the number of outstanding DMA buffers any single destination can be using. This will allow the client to set a max buffer count after opening a channel on the driver. The end result is a flow control signal which extends outside of the dma engine to the mux point for a set of streams.

In order to accomplish this we need to communicate this per dest pause to the mux stage. Here I propose adding a destPause vector to the AxiStreamCtrl record and using this record in the AxiStreamMux device.

Release Candidate v2.7.0
Author: Larry Ruckman [email protected]
Date: Thu Jul 16 16:30:55 2020 -0700
Pull: #708 (546 additions, 72 deletions, 14 files changed)
Branch: slaclab/pre-release
Issues: #707, #710, #711, #712, #713, #709, #715, #717

Notes:

New Features

  • Allow per destination buffer limits in DMA engine #707
    • AxiStreamDmaV2Desc.vhd Updates #710
  • Adding SlvDelayRam.vhd #711

Bug Fixes

  • Fix AXI-Lite protocol error in AxiLiteCrossbar #712
  • Bug fixes for UartTx.vhd & ClinkUart.vhd #713
  • Bug fixes for _EM22xx.py #709
  • Removing Accidental Commit of Python Debugger By User #715
  • Fixed typo in ClinkChannel.py #717

Update _EM22xx.py
Author: Larry Ruckman [email protected]
Date: Fri Jul 10 16:05:47 2020 -0700
Pull: #709 (1 additions, 1 deletions, 1 files changed)
Branch: slaclab/EM22xx-patch

Notes:

Description

  • Fixed the DUTY_CYCLE units
    • From kHz to %

AxiStreamDmaV2Desc.vhd Updates
Author: Larry Ruckman [email protected]
Date: Fri Jul 10 16:09:43 2020 -0700
Pull: #710 (74 additions, 43 deletions, 1 files changed)
Branch: slaclab/DmaV2-dev

Notes:

Description

  • implementing intHoldoff and idBuff with DSP primatives
    • Helps with making timing
  • reset idBuffCount if DMA disabled
    • Plus some code clean up on resetting counters/indexs when DMA disabled
  • bug fixes for intHoldoffCount=intHoldoff and idBuffCount=idBuffThold
    • Specifically fixes the issue where BG[X].Count = BG[X].Threshold + 1 when asserting pause
  • Removing roll over or roll underconditions in idBuffCount
    • should NEVER happen and don't want to mask out or hide a potential problem

Adding SlvDelayRam.vhd
Author: Larry Ruckman [email protected]
Date: Tue Jul 14 13:51:51 2020 -0700
Pull: #711 (309 additions, 0 deletions, 2 files changed)
Branch: slaclab/SlvDelayRam
Issues: #714

Notes:

Description

  • Similar to SlvDelay.vhd but with support for inferring LUTRAM, BRAM or URAM

Fix AXI-Lite protocol error in AxiLiteCrossbar
Author: Larry Ruckman [email protected]
Date: Thu Jul 16 12:25:07 2020 -0700
Pull: #712 (16 additions, 10 deletions, 1 files changed)
Branch: slaclab/axil-xbar-fix
Issues: #706

Notes:

Description

The AXI-Lite spec requires that the address cycle complete before the data cycle is initiated. The AxiLiteCrossbar was violating this rule on its slave side for both reads and writes, but only in the case of decode errors. In that case, the data response was being sent concurrent with the address acknowledge. This is now fixed.

Related

This is a fix for #706

Bug fixes for UartTx.vhd & ClinkUart.vhd
Author: Larry Ruckman [email protected]
Date: Mon Jul 13 17:39:20 2020 -0700
Pull: #713 (19 additions, 8 deletions, 2 files changed)
Branch: slaclab/clink-uart-patch

Notes:

Description

  • bug fix for UartTx.vhd baud rate
  • bug fix for ClinkUart baud rate generation

Removing Accidental Commit of Python Debugger By User
Author: Larry Ruckman [email protected]
Date: Wed Jul 15 15:31:23 2020 -0700
Pull: #715 (0 additions, 4 deletions, 1 files changed)
Branch: slaclab/ClinkSerialTx-pdb-removal

Notes:

Description

  • ClinkSerialTx is the general class and should be sub-class if the user wants to add custom debugger break point with strings that start with '@sn?'

Fixed typo in ClinkChannel.py
Author: Larry Ruckman [email protected]
Date: Wed Jul 15 15:31:13 2020 -0700
Pull: #717 (1 additions, 1 deletions, 1 files changed)
Branch: slaclab/FrameMode-description

Notes:

Description

  • Fixed typo in the FrameMode's description
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Patch Release v2.6.7

25 Jun 17:42
@ruck314 ruck314
v2.6.7
5e5bbf2
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Patch Release v2.6.7

Pull Requests Since v2.6.6

Unlabeled

  1. #705 - Release Candidate v2.6.7
  2. #704 - Another ESCRYODET-671 development Update

Pull Request Details

Another ESCRYODET-671 development Update
Author: Larry Ruckman [email protected]
Date: Thu Jun 25 10:15:49 2020 -0700
Pull: #704 (21 additions, 55 deletions, 1 files changed)
Branch: slaclab/ESCRYODET-671
Jira: https://jira.slac.stanford.edu/issues/ESCRYODET-671

Notes:

Description

  • Updates for deterministic latency startup reliability

Release Candidate v2.6.7
Author: Larry Ruckman [email protected]
Date: Thu Jun 25 10:37:50 2020 -0700
Pull: #705 (21 additions, 55 deletions, 1 files changed)
Branch: slaclab/pre-release
Issues: #704

Notes:

Description

  • Another ESCRYODET-671 development Update #704
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