Patch Release v2.24.3

Pull Requests Since v2.24.2

Unlabeled

1. #903 - Release Candidate v2.24.3
2. #902 - bug fixes for ethernet/Caui4Core/gtyUltraScale+
3. #901 - adding MicroblazeBasicCore support for 2021.1

Pull Request Details

adding MicroblazeBasicCore support for 2021.1

Author:	Larry Ruckman [email protected]
Date:	Wed Sep 15 09:55:17 2021 -0700
Pull:	#901 (471 additions, 3 deletions, 3 files changed)
Branch:	slaclab/ESCORE-674
Jira:	https://jira.slac.stanford.edu/issues/ESCORE-674

Notes:

Note

• I am using .TCL file (instead of .bd) for 2021.1 (or later) because load time is much, much faster

---

bug fixes for ethernet/Caui4Core/gtyUltraScale+

Author:	Larry Ruckman [email protected]
Date:	Thu Sep 30 10:25:54 2021 -0700
Pull:	#902 (512 additions, 58 deletions, 6 files changed)
Branch:	slaclab/htsp-dev

Notes:

Description

• ethernet/Caui4Core/gtyUltraScale+ used for HTSP protocol
• upgrading ethernet/Caui4Core/gtyUltraScale+ from 2019.1 to 2021.1

All bug fixes since 2019.1 release until 2021.1

2021.1: Version 3.1 (Rev. 4)

• Bug Fix: Added watchdog timer reset logic for RX datapath only instead of RX and TX
• Bug Fix: Updated the missing connections on the tx_preamble and rx_preamble signals within the LBUS2AXIS and AXIS2LBUS module for GT in example design configuration
• Bug Fix: Fixed the rx_preamble alignment issue with the 1st RX_TDATA and RX_TVALID for the AXIS mode configuration

2020.3: Version 3.1 (Rev. 3)

• Bug Fix: Fixed the ANLT status registers read to get the actual value with two reads

2020.1: Version 3.1

• Bug Fix: Removed timing constraints from the OOC XDC
• Bug Fix: Updated the watchdog timer logic
• Bug Fix: Updated the CMAC core location for GTM Dual X0Y11
• Bug Fix: Fixed the parallel AXI4-lite read-write issue

2019.2: Version 3.0

• Bug Fix: Updated the missing ANLT ctl ports with AXI4 lite config to the core
• Bug Fix: Updated the axis_tx and axis_rx interfaces for TX OTN interface enabled configuration
• Bug Fix: Updated the GT group selection for caui4 configuration for xcvu13p-flga2577 devices

2019.1.1: Version 2.6 (Rev. 1)

• Bug Fix: Updated the latest reset sequences from the GTM reset module for 100GAUI2 and CAUI4_GTM configuration
• Bug Fix: Fixed the stat_rx_aligned and other stat_rx signals visibility for AXIS user interface configuration

---

Release Candidate v2.24.3

Author:	Larry Ruckman [email protected]
Date:	Thu Sep 30 12:32:08 2021 -0700
Pull:	#903 (983 additions, 61 deletions, 9 files changed)
Branch:	slaclab/pre-release
Issues:	#901, #902

Notes:

Description

• #901
• #902

---

Patch Release v2.24.2

Pull Requests Since v2.24.1

Unlabeled

1. #900 - Release Candidate v2.24.2
2. #897 - whitespace removal
3. #898 - Bug fix for rxResetDoneOut when RX clock goes away
4. #899 - Fix invalid characters in Qsfp and Sfp DateCode description.

Pull Request Details

whitespace removal

Author:	Larry Ruckman [email protected]
Date:	Tue Aug 24 14:47:25 2021 -0700
Pull:	#897 (8 additions, 8 deletions, 1 files changed)
Branch:	slaclab/whitespace-removal

Notes:

Description

• generic whitespace removal

---

Bug fix for rxResetDoneOut when RX clock goes away

Author:	Larry Ruckman [email protected]
Date:	Wed Sep 8 11:13:39 2021 -0700
Pull:	#898 (9 additions, 3 deletions, 3 files changed)
Branch:	slaclab/gtx7-rxResetDoneOut-bug-fix

Notes:

Description

• Gtx7RxRst_Inst.Synchronizer_RXRESETDONE can potentially be HIGH if the clock is removed before the rxResetDone = 0x0 has propagated through the pipeline
  • I have observed this in my hardware testing
• This patch makes sure that the GTX7's rxResetDone is gated with the GTX7's RST FSM output such that rxResetDoneOut = 0x0 if rxResetDone = 0x0

---

Fix invalid characters in Qsfp and Sfp DateCode description.

Author:	Larry Ruckman [email protected]
Date:	Thu Sep 2 18:08:37 2021 -0700
Pull:	#899 (4 additions, 4 deletions, 2 files changed)
Branch:	bhill-slac/unicode-fix

Notes:

Replaces some unicode only characters w/ ascii compatible characters.

Description

Avoids an exception being thrown when we call rogue's saveAddressMap() function.

Details

Looks like a cut/paste from a vendor description. The apostrophe is a unicode slanted apostrophe
instead of the standard ascii apostrophe.

---

Release Candidate v2.24.2

Author:	Larry Ruckman [email protected]
Date:	Wed Sep 8 14:18:32 2021 -0700
Pull:	#900 (21 additions, 15 deletions, 6 files changed)
Branch:	slaclab/pre-release
Issues:	#897, #899, #898

Notes:

Description

• #897
• #899
• #898

---

Patch Release v2.24.1

Pull Requests Since v2.24.0

Unlabeled

1. #896 - Release Candidate v2.24.1
2. #809 - Optimize ZMQ channel creation in RogueTcpStreamWrap
3. #894 - Fix Ad9249.py
4. #895 - Bugfix in RogueTcpStreamWrap

Pull Request Details

Optimize ZMQ channel creation in RogueTcpStreamWrap

Author:	Larry Ruckman [email protected]
Date:	Tue Aug 10 14:40:46 2021 -0700
Pull:	#809 (69 additions, 29 deletions, 3 files changed)
Branch:	slaclab/rogue-tcp-stream-wrap

Notes:

Description

This change allows a new CHAN_MASK_G : slv(7 downto 0) flag to be passed to RogueTcpStreamWrap, to indicate which TDEST bits are expected to be active. The module then instantiates only enough RogueTcpStream instances for the number of possible TDESTs.

Note that the RogueTcpStream port numbers retain the same offset as before according to their corresponding TDEST. The following instantiation will create two RogueTcpStreams, one on port 10000 and the other on port 10256, with TDESTS X"00" and X"80" respectively.

      U_RogueTcpStreamWrap_1 : entity surf.RogueTcpStreamWrap
         generic map (
            TPD_G         => TPD_G,
            PORT_NUM_G    => 10000,
            SSI_EN_G      => true,
            CHAN_MASK_G  => "10000000",          
            AXIS_CONFIG_G => AXIS_CONFIG_C)
         port map (
            axisClk     => ethClk,         -- [in]
            axisRst     => ethRst,         -- [in]
            sAxisMaster => rogueIbMaster,  -- [in]
            sAxisSlave  => rogueIbSlave,   -- [out]
            mAxisMaster => rogueObMaster,  -- [out]
            mAxisSlave  => rogueObSlave);  -- [in]

Details

This change is backward compatible with previous versions. The module will use CHAN_COUNT_G to determine the number of channels if CHAN_MASK_G is X"00", which is the default. If CHAN_MASK_G is non-zero, then it overrides CHAN_COUNT_G and the actual channel count is determined by the number of CHAN_MASK_G bits that are set.

---

Fix Ad9249.py

Author:	Larry Ruckman [email protected]
Date:	Fri Aug 6 15:50:08 2021 -0700
Pull:	#894 (3 additions, 3 deletions, 1 files changed)
Branch:	slaclab/ePix10ka-devel

Notes:

Description

• Fixing broken python code for the AD9249 configuration.

---

Bugfix in RogueTcpStreamWrap

Author:	Larry Ruckman [email protected]
Date:	Sat Aug 14 16:23:46 2021 -0700
Pull:	#895 (1 additions, 1 deletions, 1 files changed)
Branch:	slaclab/rogue-tcp-stream-wrap

Notes:

Description

CHAN_MASK_C was being calculated incorrectly when done based on CHAN_COUNT_G.

---

Release Candidate v2.24.1

Author:	Larry Ruckman [email protected]
Date:	Fri Aug 20 11:24:17 2021 -0700
Pull:	#896 (72 additions, 32 deletions, 4 files changed)
Branch:	slaclab/pre-release
Issues:	#894, #809, #895

Notes:

Description

• #894
• #809
• #895

---

Minor Release v2.24.0

Pull Requests Since v2.23.6

Unlabeled

1. #890 - Release Candidate v2.24.0
2. #805 - Add support for AD9681 ADC
3. #888 - adding AxiStreamRingBuffer FW/SW
4. #891 - Bug fix for ad9681 and AxiStreamRingBuffer Update
5. #889 - switching to 'getFpgaArch' proc for fpga type casing
6. #893 - Updating all pyrogue memory devices
7. #892 - bug fix for HtspCaui4GtyTb

Pull Request Details

Add support for AD9681 ADC

Author:	Benjamin Reese [email protected]
Date:	Wed Aug 4 12:29:29 2021 -0700
Pull:	#805 (2281 additions, 0 deletions, 11 files changed)
Branch:	slaclab/ad9681
Issues:	#803, #804

Notes:

Description

This PR adds deserialization and configuration modules for the AD9681 ADC.

Details

JIRA

Related

#803 and #804 need to be merged first.

---

adding AxiStreamRingBuffer FW/SW

Author:	Larry Ruckman [email protected]
Date:	Tue Aug 3 14:04:05 2021 -0700
Pull:	#888 (566 additions, 0 deletions, 3 files changed)
Branch:	slaclab/AxiStreamRingBuffer

Notes:

Description

• Similiar to AxiLiteRingBuffer
  • But instead of the SW having to poll each sample from the ring buffer, this module creates an ASYNC AXI stream frame when a ring buffer event happens
• Designed to connect to a DMA or a streaming communication layer

---

switching to 'getFpgaArch' proc for fpga type casing

Author:	Larry Ruckman [email protected]
Date:	Fri Aug 6 12:52:33 2021 -0700
Pull:	#889 (57 additions, 71 deletions, 23 files changed)
Branch:	slaclab/getFpgaArch

Notes:

Description

• Reduces the number of cases that we need to support in ruckus.tcl with respect to defense grade variants

---

Release Candidate v2.24.0

Author:	Larry Ruckman [email protected]
Date:	Fri Aug 6 13:12:07 2021 -0700
Pull:	#890 (2981 additions, 77 deletions, 44 files changed)
Branch:	slaclab/pre-release
Issues:	#888, #805, #889, #891, #892, #893

Notes:

Description

• #888
• #805
• #889
• #891
• #892
• #893

---

Bug fix for ad9681 and AxiStreamRingBuffer Update

Author:	Larry Ruckman [email protected]
Date:	Thu Aug 5 15:52:51 2021 -0700
Pull:	#891 (136 additions, 74 deletions, 4 files changed)
Branch:	slaclab/AxiStreamRingBuffer-mode

Notes:

Description

• AnalogDevices/ad9681 does not support Ultrascale yet
• adding a burst and continous mode to AxiStreamRingBuffer

---

bug fix for HtspCaui4GtyTb

Author:	Larry Ruckman [email protected]
Date:	Fri Aug 6 12:52:39 2021 -0700
Pull:	#892 (1 additions, 1 deletions, 1 files changed)
Branch:	slaclab/ESCORE-671
Jira:	https://jira.slac.stanford.edu/issues/ESCORE-671

Notes:

Description

• MEMORY_TYPE_G should be "ultra" (not "uram")

---

Updating all pyrogue memory devices

Author:	Larry Ruckman [email protected]
Date:	Thu Aug 5 15:11:59 2021 -0700
Pull:	#893 (14 additions, 5 deletions, 6 files changed)
Branch:	slaclab/ESCORE-643
Jira:	https://jira.slac.stanford.edu/issues/ESCORE-643

Notes:

Description

• Setting hidden=True as default because this is what being done in every application code

---

Patch Release v2.23.6

Pull Requests Since v2.23.5

Unlabeled

1. #887 - Release Candidate v2.23.6

Pull Request Details

Release Candidate v2.23.6

Author:	Larry Ruckman [email protected]
Date:	Wed Jul 28 20:30:35 2021 -0700
Pull:	#887 (26 additions, 11 deletions, 9 files changed)
Branch:	slaclab/salt-ultrascale-plus

Notes:

Description

• Bug fix for SaltCore with Ultrascale+
• exposing SIM_DEVICE_G to top level of SaltCore
  • SIM_DEVICE_G must be "ULTRASCALE_PLUS" for Ultrascale+ else I get a router error in Vivado
  • https://forums.xilinx.com/t5/Versal-and-UltraScale/XAPP1315-LVDS-Source-Synchronous-7-1-Serialization-and/td-p/914461

---

Patch Release v2.23.5

Pull Requests Since v2.23.4

Unlabeled

1. #886 - Release Candidate v2.23.5

Pull Request Details

Release Candidate v2.23.5

Author:	Larry Ruckman [email protected]
Date:	Sat Jul 24 20:47:35 2021 -0700
Pull:	#886 (30 additions, 0 deletions, 1 files changed)
Branch:	slaclab/ESLMPS-139
Issues:	#882
Jira:	https://jira.slac.stanford.edu/issues/ESLMPS-139

Notes:

Add missing bandwidth register to AxiStreamMonAxiL.yaml, based on its pyrogue definition.

Description

We added the YAML definition for the AxiStreamMonAxiL module in #882, but the Bandwidth related register were missing. This PR adds those missing definitions.

JIRA

ESLMPS-139

Related

#882

---

Patch Release v2.23.4

Pull Requests Since v2.23.3

Unlabeled

1. #885 - Release Candidate v2.23.4

Pull Request Details

Release Candidate v2.23.4

Author:	Larry Ruckman [email protected]
Date:	Thu Jul 22 10:59:33 2021 -0700
Pull:	#885 (9 additions, 6 deletions, 4 files changed)
Branch:	slaclab/clink-full_mode_bug-fix

Notes:

Description

• Bug fix for clink using 'FULL' and '8-tap' mode

---

Patch Release v2.23.3

Pull Requests Since v2.23.2

Unlabeled

1. #884 - Release Candidate v2.23.3
2. #883 - Clink Software Update

Pull Request Details

Clink Software Update

Author:	Larry Ruckman [email protected]
Date:	Wed Jul 21 09:34:28 2021 -0700
Pull:	#883 (943 additions, 10 deletions, 6 files changed)
Branch:	slaclab/clink-ImperxC1921

Notes:

Description

• adding Imperx C1921 clink support

---

Release Candidate v2.23.3

Author:	Larry Ruckman [email protected]
Date:	Wed Jul 21 10:19:47 2021 -0700
Pull:	#884 (943 additions, 10 deletions, 6 files changed)
Branch:	slaclab/pre-release
Issues:	#883

Notes:

Description

• #883

---

Patch Release v2.23.2

Pull Requests Since v2.23.1

Unlabeled

1. #881 - Release Candidate v2.23.2
2. #882 - Add CPSW YAML definition for the AxiStreamMonAxiL module
3. #880 - Epix10ka devel changes

Pull Request Details

Epix10ka devel changes

Author:	Larry Ruckman [email protected]
Date:	Thu Jul 15 11:14:50 2021 -0700
Pull:	#880 (9 additions, 22 deletions, 2 files changed)
Branch:	slaclab/ePix10ka-devel

Notes:

Fixing 2 issues:

1. SaciMultiPixel.vhd and SaciMultiPixelPkg.vhd is only intended for the oldest ePix100a. Removing version dependency for all other ASIC types. SaciMultiPixelPkg.vhd was causing the VCS simulation to fail.

SaciMultiPixel.vhd and SaciMultiPixelPkg.vhd is an attempt to port the ePix100a bug workaround (matrix programming). This was originally implemented by Kurtis and Jack and it exists in the old firmware release used by LCLS DAQ. This port was never tested as it is not required for newer ASICs like the ePix10ka. The SaciMultiPixel procedure can be easily implemented in the DAQ software. My recommendation is to remove those two files from surf and one instance (U_SaciMultiPixel) from the EpixCoreGen2.vhd.

2. Commenting out part of the code in the _Ad9249.py causing an error (No bulkOpEn field).

---

Release Candidate v2.23.2

Author:	Larry Ruckman [email protected]
Date:	Tue Jul 20 13:00:06 2021 -0700
Pull:	#881 (240 additions, 22 deletions, 3 files changed)
Branch:	slaclab/pre-release
Issues:	#880, #882

Notes:

Description

• #880
• #882

---

Add CPSW YAML definition for the AxiStreamMonAxiL module

Author:	Larry Ruckman [email protected]
Date:	Tue Jul 20 08:39:18 2021 -0700
Pull:	#882 (231 additions, 0 deletions, 1 files changed)
Branch:	slaclab/ESLMPS-135
Jira:	https://jira.slac.stanford.edu/issues/ESLMPS-135

Notes:

Add the CPSW YAML register definition for the AxiStreamMonAxiL modules following it's pyrogue python definition

JIRA

https://jira.slac.stanford.edu/browse/ESLMPS-135

---

Patch Release v2.23.1

Description

• Patch release to fix the Github Action's anaconda building